3D Memory Gate Stack Connections That Prevent Collapse

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Solution Overview

Problem

Integrated circuit devices with 3-dimensional nonvolatile memory devices face challenges in achieving high electrical connection reliability due to the complexity of vertical memory cell arrangements and the need for efficient gate stack structures that prevent structural collapse during fabrication.

Innovation Solution

The integrated circuit device incorporates a gate stack with gate electrodes arranged vertically, featuring gate connection openings with gate connection structures that cover inner side surfaces and are connected to gate electrodes, along with channel structures and dummy structures to support the gate stack and prevent collapse during etching processes, allowing for reliable electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If 3-dimensional nonvolatile memory devices are used to achieve high integration, then the degree of integration is improved, but electrical connection reliability deteriorates

Engineering Contradiction:
Improvedegree of integrationVSAvoidelectrical connection reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Dummy structures are formed in advance within the gate connection openings before the gate connection structures are deposited. These preliminary structures serve as support during subsequent fabrication processes, preventing gate stack collapse and ensuring reliable electrical connections from the outset.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Gate connection structures are introduced as intermediary elements that bridge the gate electrodes and the upper connection structures. These intermediaries provide both mechanical support to prevent collapse and electrical connection pathways, resolving the reliability issue while maintaining high integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If gate connection structures are added to cover inner side surfaces of gate connection openings, then electrical connection reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate connection structures serve multiple functions simultaneously: they provide electrical connection between gate electrodes and upper connections, and they act as mechanical support structures to prevent gate stack collapse. This multi-functionality improves reliability without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The electrical connection function and mechanical support function are merged into a single gate connection structure. By combining these functions, the patent avoids adding separate complex structures, thus improving reliability while limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Stability of the object's composition

If dummy structures are arranged in gate connection openings, then gate stack collapse is prevented during fabrication, but manufacturing precision requirements increase

Engineering Contradiction:
Improvegate stack stabilityVSAvoidfabrication precision
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

Dummy structures are placed locally and selectively within the gate connection openings rather than uniformly throughout the device. This localized approach provides structural support precisely where needed during fabrication, maintaining gate stack stability while minimizing the overall impact on manufacturing precision requirements.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4395496A1Integrated circuit device
Publication Date: 2024.07.03 SAMSUNG ELECTRONICS CO LTD
  • EP4395496A1 patent drawingFigure 1
  • EP4395496A1 patent drawingFigure 2
  • EP4395496A1 patent drawingFigure 3

AI summary

Disclosed is an integrated circuit device. The integrated circuit device includes a substrate including a memory cell area and a connection area, a gate stack including a plurality of gate electrodes apart from each other in a vertical direction on the substrate, a plurality of gate connection openings arranged in the connection area to extend inward from an upper surface of the gate stack, one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings, a plurality of gate connection structures respectively covering at least inner side surfaces of the plurality of gate connection openings, each of the plurality of gate connection structures being connected with the one gate electrode, and a plurality of gate contacts respectively connected to upper ends of the plurality of gate connection structures.