Word Line Holding in Memory Arrays to Cut Program Verification Errors
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Solution Overview
Problem
In nonvolatile memory devices, the potential difference between selected and unselected word lines during program and verification operations can lead to errors and inefficient power consumption due to unoptimized voltage levels.
Innovation Solution
A memory device and method that includes a word line holding operation and adjusts voltage levels based on the state of unselected word lines, applying different voltages during program and verification loops to optimize power usage and reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program pulse with high voltage is applied to a selected word line to perform program operation, then the program operation can be performed effectively, but a large potential difference is created between selected and unselected word lines causing errors and power consumption issues
Solution Approach 1:
The patent applies different voltage levels to unselected word lines based on their state (program state or erase state) and their position relative to the selected word line. During program operation, unselected word lines in program state receive a first voltage level while those in erase state receive a second voltage level, dynamically adjusting parameters to reduce potential differences and power consumption while maintaining program operation accuracy
Solution Approach 2:
The patent applies different voltage levels to different groups of unselected word lines based on their local state and position. Word lines are classified into program state and erase state groups, and further differentiated by their physical relationship to the selected word line, allowing localized voltage optimization that reduces overall power consumption while preventing errors in specific regions
2Loss of energy
If different voltage levels are applied to unselected word lines based on their state, then power consumption is reduced, but the device complexity increases due to multiple voltage generation and control circuits
Solution Approach 1:
The voltage generation circuit is designed to generate multiple voltage levels (first voltage level for program state unselected word lines, second voltage level for erase state unselected word lines, and third voltage level for selected word line) using a unified multi-functional architecture. This universal voltage generation approach reduces the need for separate dedicated circuits for each voltage level, thereby reducing overall device complexity while achieving power consumption reduction
3Speed
If verification operation is performed immediately after voltage application operation, then operation speed is maintained, but errors may occur due to residual potential differences between word lines
Solution Approach 1:
The patent applies different voltage levels to unselected word lines during the voltage application operation as a preliminary action before verification. By pre-adjusting the voltage levels of unselected word lines based on their state (program or erase) before the verification operation begins, the potential differences are reduced in advance, preventing verification errors while maintaining operation speed through the streamlined voltage application process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces power consumption and minimizes errors by optimizing voltage levels applied to unselected word lines during program and verification operations.
Implementation Method 1
the potential level of a program voltage that is applied to a word line selected as a program target and the potential level of a program pass voltage that is applied to a word line not selected as a program target may be very great. Accordingly, even after timing at which the voltage application operation has been completed, the potential level of the word line selected as a program target and the potential level of a word line not selected as a program target may be in the state in which the potential levels have some degree of difference.
Data Source
AI summary
A memory device including: a memory device may include: a memory cell array, and a controller configured to perform program loops each comprising a voltage application operation, a word line holding operation, and a verification operation until a program operation for selected memory cells is successful, during the word line holding operation, apply a holding pass voltage having a higher level than a ground voltage to each of first word lines having a program state and second word lines having an erase state, which belong to unselected word lines among a plurality of word lines, during the verification operation, apply a verification pass voltage having a higher level than the holding pass voltage to K word lines that belong to the first word lines and the second word lines, and apply the holding pass voltage to remaining word lines except the K word lines, among the second word lines.