DRAM Hybrid Refresh Mode Segmentation
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) scaling increases the number of weak retention rows, leading to higher refresh cycles, which impact performance and power consumption in System on Chip (SoC) and other computer architectures, potentially resulting in DRAM chip yield loss without increased refresh cycles.
Innovation Solution
Configuring a DRAM die to operate in a hybrid refresh mode where an inactive portion operates in self-refresh mode controlled by a local DRAM die controller, and an active portion operates in controller-managed refresh mode, allowing for optimized power usage and reduced refresh cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM scaling increases the total number of bits per chip, then memory capacity is improved, but the number of weak retention rows increases leading to higher refresh cycles and power consumption
Solution Approach 1:
The patent divides the DRAM chip into multiple regions with different refresh modes. Specifically, it segments the memory array into regions that can operate in either self-refresh mode or controller-managed refresh mode, allowing weak retention rows to receive additional refresh cycles while strong retention rows use lower-power modes, thus resolving the contradiction between capacity and power consumption
Solution Approach 2:
The patent applies different refresh characteristics to different regions of the DRAM chip based on their retention properties. Weak retention rows are identified and assigned to regions with higher refresh rates, while strong retention rows use regions with lower refresh rates or self-refresh mode, optimizing power consumption locally rather than uniformly across the entire chip
2Reliability
If refresh cycles are increased to maintain data integrity in weak retention rows, then reliability is improved, but performance and power consumption deteriorate
Solution Approach 1:
The patent segments the refresh operation into different modes: self-refresh mode for regions with strong retention where data integrity is maintained with minimal interference to performance, and controller-managed refresh mode for regions with weak retention rows where additional refresh cycles are applied only when needed, thus preserving both reliability and performance
Solution Approach 2:
The patent enables self-refresh mode where the DRAM controller on-chip autonomously manages refresh operations for regions with strong retention rows without requiring external controller intervention. This self-service mechanism maintains data integrity while minimizing performance impact by operating independently of the main memory access pipeline
3Reliability
If refresh cycles are increased to maintain data integrity in weak retention rows, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements local quality by assigning different refresh modes to different regions based on their retention characteristics. Regions containing weak retention rows are configured with higher refresh rates to ensure data integrity, while regions with strong retention rows use lower refresh rates or self-refresh mode, thereby minimizing overall power consumption while maintaining reliability where needed
Solution Approach 2:
The patent changes the refresh parameter (refresh rate) dynamically based on the retention characteristics of different regions. By adjusting the refresh rate parameter locally rather than using a uniform rate across the entire chip, the system maintains data integrity in weak retention rows while reducing power consumption in strong retention rows
Data Source
AI summary
In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.