3D Memristor Synaptic Array for Parallel Neuromorphic Computing

The patent transitions from a two-dimensional synaptic array to a three-dimensional structure by stacking multiple layers of electrode pads and resistive memory elements vertically. This dimensional change enables significantly higher integration density by utilizing the third dimension (height) for additional memory cells and synaptic weights, effectively multiplying the storage capacity without increasing the planar footprint.

The patent implements a nested structure where multiple cell strings are arranged within a single synaptic array block, and multiple synaptic array blocks are stacked vertically. Each layer contains electrode pads, string select transistors, and bit lines that are interconnected through vertical vias, creating a compact nested architecture that maximizes space utilization.

The patent divides the synaptic array into multiple independent cell strings, where each cell string contains a series connection of resistive memory elements. This segmentation allows the storage capacity to be scaled by increasing the number of cell strings and the number of memory elements per string, while each individual string can be manufactured and tested separately, managing complexity through modular design.

The patent employs a universal cell string design that can be replicated across multiple layers and positions in the three-dimensional array. Each cell string follows the same structural pattern with string select transistors, resistive memory elements, and interconnect structures, allowing standardized manufacturing processes to be applied uniformly throughout the device, thereby reducing the impact of increased quantity on manufacturing precision requirements.

The patent implements dynamic control of individual layers through string select transistors positioned at different vertical levels. Each transistor can be independently activated to enable or disable specific layers of the synaptic array, allowing flexible configuration for different computational tasks. This dynamic control mechanism provides adaptability by enabling selective activation of computational layers without requiring physical reconfiguration.

The string select transistors act as intermediary control elements between the control circuitry and the resistive memory elements. These transistors serve as switches that mediate the flow of current through specific cell strings, enabling independent selection and control of different layers. This intermediary structure provides a manageable interface for controlling the complex three-dimensional array, reducing the direct control complexity.

The patent enables continuous parallel computation across multiple layers by maintaining active computational paths through the three-dimensional array. Word line selection signals can simultaneously activate multiple layers, allowing computations to proceed continuously in parallel without sequential processing delays. This continuity of useful action maximizes productivity by keeping all activated layers engaged in computation throughout the operational cycle.

The patent implements local quality control by allowing different layers to be activated or deactivated based on specific computational requirements. Word line selection signals can target specific layers or groups of layers, enabling energy-efficient computation by activating only the necessary portions of the array. This localized activation reduces overall energy consumption while maintaining high productivity in the active regions through parallel processing.