Non-Volatile Memory Page Buffer State Discrimination
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Solution Overview
Problem
Non-volatile memory devices face challenges in efficiently performing verifying read operations across memory cells with different logic states, leading to errors and increased data transfer operations due to the complexity of threshold voltage distributions and state discrimination.
Innovation Solution
The implementation of a non-volatile memory device with a memory cell array and page buffers that perform verifying read operations on memory cells, where the page buffers arrange and memorize data such that the number of low-level values among level values representing program states of one memory cell is equal to or smaller than those of another, allowing for reduced data transfer operations and error reduction by precharging memory cells simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verifying read operations are performed on memory cells with different logic states using conventional methods, then state discrimination can be achieved, but the number of data transfer operations increases and errors occur due to threshold voltage distribution complexity
Solution Approach 1:
The verifying read operation is segmented into two distinct phases: a first verifying read operation for memory cells in a first logic state and a second verifying read operation for memory cells in a second logic state. This segmentation allows each operation to be optimized for its specific state, improving discrimination accuracy while reducing overall data transfer complexity by handling each state separately rather than attempting to verify all states simultaneously
Solution Approach 2:
The method performs preliminary actions by conducting the first verifying read operation on memory cells in the first logic state before performing the second verifying read operation on memory cells in the second logic state. This preliminary verification allows the system to establish baseline data and reduce subsequent data transfer operations by only transferring data that requires further verification, thereby reducing the total number of data transfer operations while maintaining accuracy
2Productivity
If conventional verifying read operations are performed without selective precharging, then all memory cells are processed uniformly, but the number of data transfer operations increases and processing time is extended
Solution Approach 1:
The method applies local quality by selectively precharging only the bit lines associated with memory cells in the first logic state during the first verifying read operation, and only the bit lines associated with memory cells in the second logic state during the second verifying read operation. This selective precharging approach optimizes each operation for its specific target state, reducing unnecessary data transfer operations and processing time compared to uniform precharging of all bit lines
Solution Approach 2:
The selective precharging acts as a preliminary action that prepares only the necessary bit lines before each verifying read operation. By precharging bit lines selectively based on the target logic state, the system avoids unnecessary precharging operations and reduces the number of data transfer operations required, thereby improving efficiency and reducing time loss
Data Source
AI summary
A non-volatile memory device includes a memory cell array having a plurality of memory cells programmable into one of multiple logic states, the plurality of memory cells disposed at intersections of a plurality of wordlines and a plurality of bitlines, and a plurality of page buffers respectively connected to the plurality of bitlines and performing verifying read operations on the plurality of memory cells. The verifying read operations are performed on a first memory cell having a target state and a second memory cell having a lower state than the target state.