Shared-Node Memory Read Isolation Using Variable Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory chips, such as DRAM, generate noise during read operations due to current flow to secondary chips, degrading signal quality.
Innovation Solution
A memory device configuration where a processor adjusts the resistance of a variable resistor in one chip to control current flow, isolating the secondary chip during read operations, thereby reducing noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor performs read operations to memory chips via a shared node, then data can be read from memory chips, but noise is generated that degrades signal quality
Solution Approach 1:
The patent applies dynamics by making the resistance of the second memory chip adjustable rather than fixed. The processor dynamically changes the resistance value based on operation type: using a first resistance value during read operations to block current flow and reduce noise, and a second resistance value during write operations to allow current flow for proper data writing. This dynamic adjustment resolves the contradiction between enabling read operations and preventing noise interference.
Solution Approach 2:
The patent changes the electrical resistance parameter of the second memory chip to control current flow characteristics. By adjusting the resistance to different values (first resistance for read, second resistance for write), the system optimizes performance for different operational modes. This parameter change allows the system to prevent noise during reads while maintaining write capability.
2Object-affected harmful factors
If a variable resistor is added to control current flow to reduce noise, then signal quality improves, but device complexity increases
Solution Approach 1:
The patent merges the variable resistor functionality directly into the memory chip structure, combining the noise reduction function with the existing memory array. Rather than adding a separate external component, the resistance control is integrated at the chip level, allowing current flow modulation without requiring additional discrete components or complex external circuitry.
Solution Approach 2:
The variable resistor acts as an intermediary element between the memory array and the external circuit. It mediates the current flow to prevent direct noise generation during read operations while still allowing proper signal transmission. This intermediary component provides a simple and effective solution that doesn't require complex system-level modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances signal quality by preventing current flow to secondary chips during read operations, minimizing noise and maintaining data integrity.
Implementation Method 1
The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node.
Data Source
AI summary
A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.