Memory Staircase Contact Structure to Prevent Stack Collapse
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Solution Overview
Problem
As vertical memory array technology advances, the stacks in memory devices are prone to toppling or collapse during processing, and the decreasing dimensions and spacing of conductive features lead to increased parasitic capacitance, causing higher power demands and delays.
Innovation Solution
The formation of staircase structures with sacrificial materials and selective etching techniques to stabilize the vertical memory arrays, reducing the risk of collapse and minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the stacks increases to facilitate additional memory cells, then memory density is improved, but the stacks become prone to toppling or collapse during processing
Solution Approach 1:
The stack structure is segmented into multiple tiers with staircase structures formed between adjacent tiers. These staircase structures act as intermediate support platforms that divide the tall stack into smaller, more stable segments, preventing toppling while maintaining high memory density
Solution Approach 2:
Sacrificial materials are introduced as intermediary structures during fabrication. These materials provide temporary support to the tall stacks during processing, and are later removed to create the final staircase structure. The sacrificial materials act as mediators that enable stack stability without compromising the final device architecture
2Quantity of substance
If the dimensions and spacing of conductive features decrease, then memory density is improved, but parasitic capacitance increases causing higher power demands and delays
Solution Approach 1:
The staircase structures create localized regions with different electrical characteristics. By strategically positioning conductive contact structures on the staircase steps, the design optimizes local electrical properties to minimize parasitic capacitance between adjacent conductive features while maintaining small overall dimensions
Solution Approach 2:
The staircase structures introduce a vertical dimension to the conductive feature arrangement. Instead of simply reducing horizontal spacing, the design uses vertical staggering to increase separation between conductive features, thereby reducing parasitic capacitance while maintaining high memory density through efficient space utilization
Data Source
AI summary
A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, conductive contacts within a horizontal area of the staircase structure and vertically extending through the stack structure to the source tier, and strapping structures laterally adjacent to the conductive contacts and having upper surfaces substantially coplanar with upper surfaces of the conductive contacts. Each of the strapping structures are in contact with one of the conductive contacts and with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.