CMOS Under-Array Architecture for 3D NAND Memory Area Reduction
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Solution Overview
Problem
As semiconductor memory technologies scale down, they face challenges such as increased variability in wire resistance and transistor characteristics due to process, voltage, and temperature variations, which affect the performance and area efficiency of non-volatile memory arrays.
Innovation Solution
The implementation of a 3D NAND memory array with vertical NAND strings and sensing circuitry positioned underneath, utilizing vertical connections through memory breaks to connect bit lines above the array to sense amplifiers, allowing for efficient data sensing and programming across multiple portions of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If sense amplifiers are positioned below the memory array with vertical connections through memory breaks, then area efficiency is improved and scalability is enhanced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from a planar arrangement where sense amplifiers are positioned to the side of memory arrays to a three-dimensional configuration where sense amplifiers are located below the memory array. Vertical connections through memory breaks enable electrical access from the bottom surface, effectively utilizing the Z-dimension to reduce the footprint area while maintaining functional connectivity.
Solution Approach 2:
The memory array is divided into multiple portions with intermediate memory breaks that segment the structure vertically. These breaks allow independent vertical connections to be formed through specific regions, enabling selective access to sense amplifiers positioned below different portions of the array without interfering with the continuous memory structure.
2Quantity of substance
If process geometries are shrunk to reduce cost per bit, then manufacturing cost is reduced, but variability in wire resistance and transistor characteristics increases
Solution Approach 1:
The patent modifies the physical and electrical parameters of the memory structure by implementing vertical connections through memory breaks. This changes the current path geometry and reduces the effective wire length in the lateral direction, thereby reducing the impact of process variability on resistance while maintaining scaled dimensions for cost efficiency.
Data Source
AI summary
Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.