Capacitorless DRAM Cell Structure for Coupling Noise Suppression
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Solution Overview
Problem
In single-transistor DRAM memory cells without a capacitor, capacitive coupling between the word line and the floating body leads to noise interference during data reading and writing, causing false readings and rewrites, making practical use challenging.
Innovation Solution
A memory device structure with a semiconductor substrate, gate insulating layers, and conductor layers with different work functions, where voltage control is used to manage electron and hole generation and accumulation through impact ionization and gate-induced drain leakage, allowing for controlled memory write and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single-transistor DRAM memory cell without a capacitor is used to achieve high integration, then device density is improved, but capacitive coupling between the word line and floating body causes noise interference and false readings
Solution Approach 1:
The patent transitions from a planar single-transistor structure to a three-dimensional stacked structure with multiple gate electrodes positioned above and below the semiconductor substrate. This vertical stacking enables higher device density while the separated gate structures reduce capacitive coupling noise by distributing the coupling effect across multiple controlled interfaces rather than a single problematic interface.
Solution Approach 2:
The single gate electrode is segmented into multiple gate electrodes (first gate electrode above the substrate, second gate electrode below the substrate). This segmentation allows independent control of each gate, enabling differential signaling and noise cancellation techniques that reduce the impact of capacitive coupling on data reading accuracy.
2Speed
If gate-induced drain leakage current is utilized for memory operation, then write speed is improved, but voltage control complexity increases
Solution Approach 1:
The patent employs dynamic voltage control where the first and second gate electrodes receive different voltages during write operations to induce drain leakage current for rapid data writing. During read operations, the voltage scheme changes to minimize leakage and measure stored data. This dynamic switching between operational modes enables high write speed while managing voltage control complexity through standardized control circuits.
Solution Approach 2:
The patent changes voltage parameters (magnitude, polarity, timing) applied to the gate electrodes depending on the operational mode (write vs. read). By dynamically adjusting these electrical parameters, the system achieves fast write speeds through controlled drain leakage while maintaining manageable complexity through systematic voltage scheduling rather than complex circuit architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces noise interference, enhances data integrity, and enables efficient operation of single-transistor DRAM cells with improved storage holding time and voltage margins, facilitating higher-density and high-performance memory devices.
Implementation Method 1
operation of generating electrons and holes in a semiconductor base material by an impact ionization phenomenon with current flowing between the first impurity layer and the second impurity layer
Implementation Method 2
operation of generating electrons and holes in a semiconductor base material by an impact ionization phenomenon with current flowing between the first impurity layer and the second impurity layer or by gate-induced drain leakage current
Data Source
AI summary
An n+ layer 3a connected to a source line SL at both ends, an n+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.