3D Memory Cell Array Layout With GAA Channels for Higher Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high density and small cell size, which are essential for advanced applications, as traditional two-dimensional circuits are limited in terms of memory cell density and efficiency.
Innovation Solution
The development of a three-dimensional memory structure with a multi-level memory cell array and gate-all-around (GAA) transistor architecture, where memory cells are stacked and interconnected with bit lines, source lines, and word lines, allowing for increased density and efficiency through advanced patterning techniques like double-patterning or multi-patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional circuits are used, then manufacturing process is simpler, but memory cell density is lower and power consumption is higher
Solution Approach 1:
The patent transitions from traditional two-dimensional circuit layouts to three-dimensional stacked memory structures. Multiple memory cell levels are stacked vertically, with each level containing memory cells formed over respective word lines. This vertical stacking enables higher memory cell density by utilizing the third dimension (height) rather than only expanding horizontally, directly resolving the contradiction between density and structural complexity.
Solution Approach 2:
The patent implements nested structures where gate electrodes wrap around channel regions in gate-all-around configurations. The gate electrodes are positioned at different heights and angles to completely surround the channel, creating a nested arrangement that improves control and density while managing structural complexity through systematic positioning.
2Quantity of substance
If cell size is reduced to increase density, then memory cell density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory structure into multiple discrete levels stacked vertically, with each level containing segmented memory cells. The memory cells are further segmented into distinct components (channel regions, gate electrodes, insulating layers) that can be independently formed and controlled. This segmentation allows for standardized fabrication processes at each level, maintaining manufacturing precision while achieving high density through vertical stacking.
Solution Approach 2:
The patent employs systematic parameter changes including varying gate electrode angles (e.g., 45 degrees, 90 degrees), different insulating layer materials (oxide-nitride-oxide, ferroelectric), and controlled channel region dimensions. These parameter variations are implemented across different levels and regions to optimize density while maintaining manufacturability through established process controls.
3Quantity of substance
If three-dimensional stacked structure is implemented, then memory cell density increases, but interconnect complexity increases
Solution Approach 1:
The patent merges multiple functions into shared structures. Bit lines and source lines are shared across multiple memory cells and levels, reducing the total number of interconnects required. Word lines are extended to serve multiple memory cells at different positions. This merging approach reduces interconnect complexity while maintaining high density by eliminating redundant connections.
Solution Approach 2:
The patent implements universal interconnect structures where certain conductive layers and lines serve multiple purposes across different memory cell levels and types. For example, some conductive layers function as both bit lines for certain cells and source lines for others, or as word lines for multiple cell arrays. This multi-functionality reduces the overall interconnect burden while supporting the three-dimensional stacked architecture.
Data Source
AI summary
A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.