Non-Volatile Memory Reliability Screening via Sensing Reference Adjustment
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Solution Overview
Problem
Conventional methods for reliability screening of EEPROM cells in embedded non-volatile memory arrays, especially those storing irregular data, are inefficient and require significant test time, often necessitating additional memory space for storing expected data patterns, which complicates the identification of the weakest cells during built-in self-test routines.
Innovation Solution
A method that determines the most stringent sensing reference level for memory cells and incrementally adjusts it to identify the weakest cell by evaluating each address until a failed read is detected, allowing for precise determination of the weakest cell's strength and address without requiring knowledge of the stored data, thus reducing test time and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used for reliability screening of EEPROM cells storing irregular data, then the screening can be performed, but it requires significant test time and additional memory space for storing expected data patterns
Solution Approach 1:
The patent applies preliminary action by pre-loading a copy of the irregular data pattern into a small on-chip memory buffer before the reliability screening process begins. This allows the test circuit to quickly compare read results against the pre-stored expected data without requiring time-consuming external memory access or regeneration of test patterns during the actual screening, thereby significantly reducing test time while maintaining full reliability screening capability
Solution Approach 2:
The patent uses copying by creating a duplicate copy of the irregular data pattern and storing it in a small on-chip memory buffer. This copy serves as the reference for comparison during reliability screening, eliminating the need to store the full expected data pattern in large external memory or to regenerate it repeatedly, thus reducing both test time and external memory space requirements
2Reliability
If conventional methods are used for reliability screening, then the screening can be performed, but it requires additional memory space for storing expected data patterns
Solution Approach 1:
The patent applies preliminary action by pre-loading a copy of the irregular data pattern into a small on-chip memory buffer before the reliability screening process begins. This allows the test circuit to quickly compare read results against the pre-stored expected data without requiring time-consuming external memory access or regeneration of test patterns during the actual screening, thereby significantly reducing test time while maintaining full reliability screening capability
Solution Approach 2:
The patent uses copying by creating a duplicate copy of the irregular data pattern and storing it in a small on-chip memory buffer. This copy serves as the reference for comparison during reliability screening, eliminating the need to store the full expected data pattern in large external memory or to regenerate it repeatedly, thus reducing both test time and external memory space requirements
3Reliability
If conventional methods are used for reliability screening, then the screening can be performed, but it complicates the identification of the weakest cells during built-in self-test routines
Solution Approach 1:
The patent applies segmentation by dividing the reliability screening process into distinct functional modules: an address generator that sequentially addresses memory cells, a read circuit that retrieves stored data, a comparator that compares read data with the pre-loaded copy in the buffer, and a weakest cell identifier that tracks and reports failing addresses. This modular segmentation simplifies the overall test routine complexity by making each component's function clear and manageable, while maintaining comprehensive reliability screening capability
Solution Approach 2:
The patent implements feedback by continuously comparing the data read from each memory cell address with the corresponding data in the pre-loaded copy stored in the on-chip buffer. When a mismatch is detected, the system immediately identifies that address as a potential weakest cell and adjusts the testing focus accordingly. This feedback mechanism simplifies the test routine by automatically guiding the identification process rather than requiring complex external analysis
Data Source
AI summary
An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a first memory address of the array, a most stringent value of a sensing reference level at which correct data are read is identified. The remainder of the addresses of the array are evaluated in sequence, beginning at the value determined for the first address, and incrementally adjusting the sensing reference level for each, if necessary, until correct data are read at that address. The sensing reference level may be a reference current applied to a sense amplifier, against which read current from the addressed memory cell is compared, or may be control gate voltage applied to the control gate of a floating-gate transistor in the addressed memory cell. The process continues until all addresses in the memory array have been evaluated, following which the reference level identifies the strength of the weakest cell in the array, and the weakest address can be identified.