NAND Memory Read Failure Mitigation via Dynamic Pass Voltage
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Solution Overview
Problem
Flash memory devices experience read failure due to decreased cell current caused by increased resistance in the NAND architecture, leading to a higher probability of read operations failing, especially for drain-side word lines.
Innovation Solution
The solution involves biasing unselected word lines with a higher Vpass—read voltage during read operations for drain-side word lines and achieving a deeper erase condition for cells closer to the drain-side of the memory block, which increases the pass gate cell current and reduces read failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND architecture is used to achieve high memory density, then memory density is improved, but read reliability deteriorates due to increased resistance and decreased cell current
Solution Approach 1:
The patent applies different pass voltages to different word lines based on their position in the memory array. Drain-side word lines receive a higher pass voltage (Vpass-read) compared to source-side word lines, compensating for the increased resistance and current loss in drain-side cells. This localized adjustment of electrical parameters resolves the read reliability issue while maintaining the high-density NAND architecture.
Solution Approach 2:
The patent changes the electrical parameters (pass voltage levels) dynamically based on the selected word line position. By adjusting Vpass-read to be higher for drain-side word lines, the system compensates for the degraded cell current without changing the physical architecture, thus maintaining both high density and read reliability.
2Quantity of substance
If drain-side word lines are used to access memory cells, then memory capacity is improved, but read current decreases due to increased resistance
Solution Approach 1:
The patent applies a counterbalancing voltage boost to drain-side word lines during read operations. The increased Vpass-read acts as an electrical counterweight that compensates for the resistive losses in the drain-side cell path, ensuring sufficient read current reaches the sense amplifiers even when accessing cells at the drain end of the array.
3Device complexity
If unselected word lines are biased at normal Vpass-read voltage, then device simplicity is maintained, but read margin decreases leading to higher read failure rate
Solution Approach 1:
The patent introduces dynamic voltage selection based on the position of the selected word line. The pass voltage for unselected word lines is adjusted dynamically - higher for drain-side word lines and normal for source-side word lines. This dynamic adaptation improves read margin and reduces read failures without requiring complete architectural redesign, balancing complexity and reliability.
Data Source
AI summary
Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.