3D NAND Channel Native Oxide Layer for Etchant Protection

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Solution Overview

Problem

Existing 3D NAND memory devices face damage to blocking layers during gate replacement processes due to etchants, which impairs their performance.

Innovation Solution

A native oxide layer is formed along the sidewalls of channel holes by oxidizing parts of the silicon nitride layers, serving as a protective layer to prevent damage from etchants and potentially acting as a blocking layer itself, with a thickness between 0.5 nm and 3 nm, formed using wet chemical oxidation with a mixture of hydrofluoric acid and ozone.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If gate replacement process is performed using conventional etchants, then conductor layers can be formed by replacing dielectric layers, but blocking layers are damaged by etchants which impairs device performance

Engineering Contradiction:
Improvegate replacement processVSAvoidblocking layer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A native oxide layer is formed on the surface of the blocking layer before the gate replacement process. This native oxide layer acts as an intermediary protective barrier that prevents conventional etchants from damaging the blocking layer during conductor layer formation, thereby maintaining blocking layer integrity while enabling the gate replacement process to proceed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The native oxide layer is formed in advance before the gate replacement process begins. This preliminary oxidation step prepares the blocking layer surface with a protective oxide coating that will shield it from subsequent etchant exposure during the conductor layer formation process

Inventive Principle:
Principle #10Preliminary action

2Reliability

If native oxide layer is formed by wet chemical oxidation using hydrofluoric acid and ozone, then blocking layers are protected from etchant damage, but additional process steps are required

Engineering Contradiction:
Improveblocking layer protectionVSAvoidfabrication process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The oxidation process uses specific chemical parameters (hydrofluoric acid concentration, ozone concentration, temperature, time) to control the formation of the native oxide layer. By optimizing these parameters, the process achieves effective blocking layer protection while managing the complexity of the additional fabrication step

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The native oxide layer effectively protects the blocking layers from etchant damage, maintaining their integrity and improving the performance and reliability of 3D NAND memory devices by acting as a protective and functional layer.

Implementation Method 1

the native oxide layer is formed by oxidizing the sidewall of channel hole including left portions of first dielectric layers to form native oxide

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

the native oxide layer is formed by wet chemical oxidation using chemicals containing ozone, wherein the wet chemical is a mixture of hydrofluoric acid and ozone

Methodology Applied
Scientific EffectWet chemical oxidation:

Data Source

PatentEP3815140B1Methods for forming three-dimensional memory device having channel structures with native oxide layer
Publication Date: 2024.02.28 YANGTZE MEMORY TECH CO LTD
  • EP3815140B1 patent drawingFigure 1A
  • EP3815140B1 patent drawingFigure 1B
  • EP3815140B1 patent drawingFigure 2A

AI summary

Embodiments of 3D memory device having channel structures with a native oxide layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack is formed on a substrate. The dielectric stack includes interleaved first dielectric layers and second dielectric layers on a substrate. An opening extending vertically through the dielectric stack is formed. A native oxide layer is formed along a sidewall of the opening. The native oxide layer includes native oxide of at least some of the first dielectric layers. A deposited oxide layer, a storage layer, a tunneling layer, and a semiconductor channel are subsequently formed in this order over the native oxide layer and along the sidewall of the opening. A memory stack includes interleaved conductor layers and the second dielectric layers is formed by replacing, with the conductor layers, the first dielectric layers in the dielectric stack.