3D Memory Stack Gate Lines With Variable Tier Thickness

The patent divides the conductive gate line formation into multiple segments: first conductive material is deposited and patterned to form initial gate lines, then second conductive material is deposited and selectively removed to create varying thickness regions. This segmentation allows optimization of conductivity in different vertical zones of the memory stack, resolving the contradiction between performance and complexity by breaking down the complex formation process into manageable stages.

The patent implements local quality by creating conductive gate lines with non-uniform thickness distribution - thicker regions provide higher conductivity where needed, while thinner regions reduce lateral space. The first and second conductive materials are selectively removed to create locally optimized thickness profiles, allowing the structure to achieve both low resistance and compact dimensions, thus resolving the performance-complexity contradiction.

The patent applies local quality by creating conductive gate lines with spatially varying thickness - thinner in regions where lateral space is critical, and thicker where conductivity is prioritized. This is achieved through selective deposition and removal processes that locally adjust the gate line profile, reducing overall lateral footprint while maintaining manufacturability through standardized deposition techniques.

The patent transitions from two-dimensional uniform thickness to three-dimensional variable thickness by depositing multiple layers of conductive material at different angles and selectively removing portions. This dimensional approach allows the gate lines to occupy less lateral space while maintaining adequate conductivity through vertical thickness variation, resolving the contradiction between area reduction and manufacturing ease.

The patent implements local quality by creating thicker conductive gate line regions only where high conductivity is required, while using thinner regions in areas where lateral space is the constraint. The selective removal of first and second conductive materials creates a non-uniform thickness profile that optimizes conductivity locally without increasing overall lateral dimensions, thus resolving the contradiction between conductivity and area.

The patent introduces asymmetry in the conductive gate line thickness distribution - rather than uniform thickness, the gate lines have asymmetric thickness profiles with varying depths in different lateral positions. This asymmetric design allows thicker sections to provide high conductivity where needed while thinner sections reduce lateral space requirements, resolving the contradiction between conductivity improvement and area reduction.