Flash Memory Annealing for Frequent Write Endurance
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Solution Overview
Problem
Program and erase operations in Flash and other floating-gate memories lead to cumulative defects in oxide insulators and charge-trapping layers, limiting their useful life and making them unsuitable for frequent write operations.
Innovation Solution
A system that performs in-situ annealing operations to extend the utility of degraded components by heating floating-gate memory cells to temperatures above the normal operating range, dislodging permanently-trapped carriers and improving longevity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Flash and floating-gate memories are used for frequent write operations, then productivity is improved, but reliability deteriorates due to cumulative defects from program and erase operations
Solution Approach 1:
The patent applies preliminary action by performing annealing operations on memory devices before they fail completely. The system proactively heats memory devices to elevated temperatures to dislodge trapped carriers and repair defects before they accumulate to a failure threshold, thereby extending the device's useful life and maintaining reliability during frequent write operations
Solution Approach 2:
The patent utilizes parameter changes by varying the temperature parameter of the memory device. By heating the memory device to an elevated temperature (above normal operating range but below maximum rated temperature), the trapped carriers gain sufficient thermal energy to escape from oxide traps and charge-trapping layers, thereby repairing defects and improving device longevity
2Reliability
If memory devices are heated to elevated temperatures for annealing, then reliability is improved by dislodging trapped carriers, but energy consumption increases
Solution Approach 1:
The patent applies periodic action by implementing annealing operations at scheduled intervals rather than continuously. The memory controller monitors usage patterns and triggers annealing operations periodically based on accumulated write operations or time elapsed, thereby achieving defect repair while minimizing unnecessary energy consumption during light usage periods
Solution Approach 2:
The patent applies discarding and recovering by temporarily sacrificing normal operational capacity during annealing to recover long-term reliability. The system enters a maintenance mode where write operations are redirected or blocked while annealing proceeds, temporarily discarding productivity to recover the memory device's longevity and performance
3Reliability
If data is evacuated from memory devices during annealing, then reliability is maintained by preventing data loss, but productivity decreases due to data transfer overhead
Solution Approach 1:
The patent applies preliminary action by evacuating data from memory devices before the annealing process begins. The memory controller identifies valid data in the memory device, reads it to a buffer or alternate storage location, and updates mapping tables before initiating the annealing operation, ensuring data is protected before any potential data loss could occur
Solution Approach 2:
The patent uses an intermediary approach by introducing a buffer memory or alternate storage device as a mediator during data evacuation. The buffer temporarily holds data being transferred from the annealing memory device, allowing the annealing process to proceed while data remains accessible through the intermediary storage, thereby maintaining system productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The annealing process effectively reverses defects in memory cells, enhancing their longevity and suitability for applications requiring frequent write operations by improving the reliability of data storage.
Implementation Method 1
by heating floating-gate memory cells to temperatures above the normal operating range, but below a tolerable maximum, otherwise permanently-trapped carriers may be dislodged from oxides and charge-trapping layers, in effect, annealing the defects
Implementation Method 2
otherwise permanently-trapped carriers may be dislodged from oxides and charge-trapping layers, in effect, annealing the defects and improving longevity
Data Source
AI summary
Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.