3D NAND Channel-String Layout for Density and Cell Isolation
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Solution Overview
Problem
Existing memory cell fabrication methods face challenges in achieving high density and efficient isolation between memory cells, particularly in three-dimensional NAND architectures, leading to suboptimal performance and density.
Innovation Solution
A method involving the formation of horizontally-spaced pairs of channel-material strings through vertically-alternating conductive and insulative tiers, with sacrificial material replacement to create conductive control-gate lines, and precise etching to enhance memory cell structure and isolation, allowing for improved cell density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell fabrication methods are used, then manufacturing simplicity is maintained, but memory cell density and lateral isolation are insufficient
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: forming insulative tiers, forming conductive tiers, forming channel-material strings between specific tiers, and selective etching. This segmentation allows for precise control of memory cell structure and isolation, achieving higher density while maintaining manufacturability through modular processing
Solution Approach 2:
The patent transitions from planar memory cell arrangements to three-dimensional vertically-stacked architectures by forming multiple tiers of conductive and insulative materials extending in the vertical dimension. This enables significantly higher memory cell density by utilizing vertical space rather than only horizontal plane
2Quantity of substance
If memory cells are closely packed to increase density, then storage capacity improves, but lateral isolation between cells deteriorates
Solution Approach 1:
The patent applies different material properties to different spatial locations: insulative tiers are positioned in specific locations between conductive tiers to provide lateral isolation where needed, while conductive tiers are positioned to enable electrical connectivity. This local differentiation of material quality allows close packing of memory cells while maintaining necessary isolation through the strategically placed insulative tiers
Solution Approach 2:
Insulative tiers act as intermediary layers between adjacent channel-material strings, providing lateral isolation. These intermediary insulative tiers are formed between specific conductive tiers and prevent electrical interference between neighboring memory cells, enabling higher density packing while maintaining signal integrity
Data Source
AI summary
A method used in forming memory circuitry comprising strings of memory cells comprising channel-material strings comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first set of horizontally-spaced pairs of channel-material strings are formed to extend through the first tiers and the second tiers. After forming the first set, a second set of horizontally-spaced pairs of channel-material strings is formed to extend through the first tiers and the second tiers. The pairs in the first set individually horizontally alternating with the pairs in the second set. Other embodiments, including structure, are disclosed.