Vertical NAND Channel Structure Using 2D Semiconductors for Cell Current
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Solution Overview
Problem
In vertical NAND (VNAND) memory devices, increasing the number of stacks to achieve higher capacity leads to difficulties in obtaining sufficient cell current due to increased cell region height, which affects data retention and access efficiency.
Innovation Solution
The use of a channel layer made from high charge mobility two-dimensional semiconductor materials like tellurene, black phosphorus, or WSe2, combined with boron nitride layers and a specific gate insulating structure, enhances electron and hole mobility, improving cell current and program speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of VNAND stacks is increased to achieve higher capacity, then storage density is improved, but cell region height increases making it difficult to obtain sufficient cell current
Solution Approach 1:
The patent changes the material parameter of the channel layer from conventional materials to two-dimensional semiconductor materials (such as MoS2, WS2, WSe2, MoSe2, black phosphorus, or tellurene), which fundamentally alters the electrical properties by providing high charge mobility. This material parameter change enables sufficient cell current even when the cell region height increases due to more stacks, thereby resolving the contradiction between storage capacity and cell current reliability.
Solution Approach 2:
The patent employs composite material structures including two-dimensional semiconductor channel layers combined with high-k dielectric materials (such as HfO2, Al2O3, TiO2, or Ta2O5) for gate insulating layers, and boron nitride layers for interface quality enhancement. This composite approach optimizes both the electrical performance for sufficient cell current and the structural integrity for high-density stacking, simultaneously addressing storage capacity and current reliability.
2Quantity of substance
If the cell region height is increased to accommodate more stacks, then storage density is improved, but program speed deteriorates due to reduced cell current
Solution Approach 1:
The patent changes the charge mobility parameter of the channel layer material to high values through using two-dimensional semiconductors, which directly improves carrier transport efficiency. This parameter change enables fast programming speed even in tall cell regions with increased stack density, as the high mobility compensates for the longer transport distance required in higher-density configurations.
Solution Approach 2:
The patent applies high-k dielectric materials specifically in the gate insulating layer adjacent to the two-dimensional semiconductor channel, creating a localized high-quality interface region. This local quality enhancement ensures efficient charge injection and extraction at critical interfaces, maintaining fast program speeds despite increased cell region height from higher stack density.
3Ease of manufacture
If conventional channel materials are used, then manufacturing is simpler, but charge mobility is insufficient leading to poor cell current
Solution Approach 1:
The patent changes the fundamental material parameter (charge mobility) by transitioning to two-dimensional semiconductor materials, which inherently possess high mobility due to their two-dimensional electronic structure and reduced scattering mechanisms. While manufacturing processes need to be adapted for these materials, the significant improvement in charge mobility parameter justifies the process complexity, achieving sufficient cell current for high-density operation.
Solution Approach 2:
The patent introduces boron nitride layers as intermediary materials between the two-dimensional semiconductor channel and adjacent dielectric layers. These intermediary layers provide high-quality interfaces that preserve the high charge mobility of the two-dimensional materials while enabling integration with conventional manufacturing processes, thus bridging the gap between advanced material properties and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases electron mobility, hole mobility, and reduces thickness, leading to improved cell current, increased stack density, and enhanced threshold voltage distribution in VNAND memory devices, supporting higher capacity and efficiency.
Implementation Method 1
The channel layer may include a two-dimensional semiconductor material having an electrically p-type property... a hole mobility of the channel layer may be greater than or equal to about 80 cm2/Vs, and an electron mobility of the channel layer may be greater than or equal to about 20 cm2/Vs
Implementation Method 2
a gate insulating layer extending in a first direction, the gate insulating layer between the channel layer and the plurality of gate electrodes
Implementation Method 3
The gate insulating layer may include a tunneling dielectric layer... The tunneling dielectric layer may be between the channel layer and the charge trap layer
Data Source
AI summary
A nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers alternately arranged with each other in the first direction, and a gate insulating layer extending in the first direction. Each of the plurality of gate electrodes and each of the plurality of spacers may extend in a second direction crossing the first direction. The gate insulating layer may extend in the first direction. The gate insulating layer may be between the channel layer and the plurality of gate electrodes. The channel layer may include a two-dimensional semiconductor material having an electrically p-type property.