Bitline Voltage Ramping for Low-Power Non-Volatile Memory Reads

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Solution Overview

Problem

Existing non-volatile memory technologies face inefficiencies in power consumption during sensing operations, particularly in transitioning bitline voltages, leading to increased power usage and potential errors.

Innovation Solution

A method is introduced where the bitline voltage is ramped down after transitioning the wordline voltage and then ramped back up before sensing, optimizing power usage and reducing errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bitline voltage is maintained at high level during wordline voltage transition, then sensing operation can proceed continuously, but power consumption increases

Engineering Contradiction:

Improvesensing operation continuityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The bitline voltage is periodically adjusted: ramped down during wordline voltage transition to reduce power consumption, then ramped back up before sensing operation to maintain functionality. This periodic adjustment optimizes the trade-off between power savings and operational continuity.

Inventive Principle:

Principle #19Periodic action

2Use of energy by moving object

If bitline voltage is ramped down during wordline transition, then power consumption is reduced, but voltage stability may be compromised

Engineering Contradiction:

Improvepower consumptionVSAvoidvoltage stability

Core Design Contradiction:

Use of energy by moving objectVSStability of the object's composition

Solution Approach 1:

The bitline voltage is ramped back up in advance before the sensing operation begins. This preliminary action ensures that the voltage is restored to the required level for stable sensing, preventing potential errors while maintaining power savings during the transition period.

Inventive Principle:

Principle #10Preliminary action

3Use of energy by moving object

If bitline voltage is rapidly ramped down, then power savings are maximized, but voltage transition time increases

Engineering Contradiction:

Improvepower savingsVSAvoidvoltage transition time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The bitline voltage transition is performed dynamically with controlled ramping rates. The voltage is ramped down at an optimized rate to maximize power savings, then ramped back up at an appropriate rate to minimize total transition time. This dynamic adjustment balances power efficiency with time constraints.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12542185B2Read power savings by temporarily disabling bitline voltage

Publication Date: 2026.02.03 SANDISK TECHNOLOGIES LLC

AI summary

A memory device includes a set of memory cells and a control circuit coupled to the set of memory cells. The control circuit is configured to transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level. While the wordline voltage settles at the second wordline voltage level, the control circuit cuts off current to the target memory cell by at least one of temporarily ramping down a bitline voltage from a first bitline voltage level to a second bitline voltage level, temporarily ramping down a select gate voltage from a first select gate voltage level to a second select gate voltage level, and temporarily ramping up a source line voltage from a first source level to a second source level.