Wrapped Floating Gate Structure for Scaled Flash Memory Cells
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Solution Overview
Problem
As flash memory cells scale down, they experience short channel effects such as drain induced barrier lowering and velocity saturation, leading to data programming inefficiency and a smaller read window due to reduced coupling ratio and charge carrier difficulty in reaching the floating gate.
Innovation Solution
The implementation of an enhanced floating gate structure with sidewalls that protrude vertically, increasing the interfacing area with the channel region, allowing easier charge carrier injection and improving data programming efficiency and read window by wrapping around the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory cells are scaled down to increase storage density, then storage capacity is improved, but short channel effects such as drain induced barrier lowering and velocity saturation occur, leading to reduced programming efficiency and smaller read window
Solution Approach 1:
The floating gate structure transitions from a planar configuration to a three-dimensional wrapped configuration that extends vertically and wraps around the channel region. This dimensional change increases the interfacing area between the floating gate and channel without increasing the planar footprint, thereby maintaining storage density while improving charge carrier coupling and programming efficiency through enhanced electric field interaction.
Solution Approach 2:
The floating gate is designed with curved surfaces that wrap around the channel region, creating a more efficient electric field distribution. This curved configuration improves the coupling ratio between the floating gate and channel, enabling better charge carrier injection and reading performance while mitigating short channel effects in scaled-down devices.
2Quantity of substance
If flash memory cells are scaled down, then storage density is improved, but the read window decreases due to reduced coupling ratio and difficulty in charge carrier injection
Solution Approach 1:
The floating gate extends into the third dimension by wrapping around the channel region, increasing the effective interfacing area without increasing the planar cell size. This enhanced three-dimensional configuration improves the coupling ratio, enabling stronger electric field effects and better charge carrier injection, which directly increases the read window in scaled-down memory cells.
Solution Approach 2:
The floating gate structure is nested around the channel region, with the gate material conformally coating the channel surfaces. This nested configuration maximizes the electric field interaction between the floating gate and channel, improving charge carrier coupling and read window while maintaining compact cell dimensions for high storage density.
3Device complexity
If a conventional planar floating gate is used, then device structure is simple, but the interfacing area with the channel region is limited, reducing charge carrier injection efficiency
Solution Approach 1:
The floating gate transitions from a two-dimensional planar structure to a three-dimensional wrapped structure that conforms to the channel region geometry. This dimensional evolution significantly increases the interfacing area between the floating gate and channel, enabling more efficient charge carrier injection and programming while maintaining a relatively simple fabrication process through conformal deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances data programming efficiency and read window by increasing the charge on the floating gate and the difference in channel conductivity between data states, thereby improving the overall performance of flash memory cells.
Implementation Method 1
the floating gate has sidewalls that define protrusions extending vertically outward from a lower surface of the floating gate. The protrusions cause the floating gate to wrap around a part of the substrate where a channel region forms, thereby increasing a size of an interfacing area between the channel region and the floating gate
Data Source
AI summary
The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.