Memory Read Voltage Modulation for Faster Soft-Bit Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems face inefficiencies in data retrieval due to shifts in threshold voltages of memory cells, leading to long latency and inefficient retry processes when decoding errors occur, especially when multiple bits are stored, and blind searching for optimized read voltages is inefficient.
Innovation Solution
The proposed solution involves reading soft bit data through boosted modulation of voltages adjacent to the read voltage to obtain XOR results, which are used in conjunction with hard bit data for improved error recovery, and scheduling the reading of both types of data together to minimize delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory systems use threshold voltage shifts for storing multiple bits, then storage capacity is improved, but data retrieval latency increases due to decoding errors and retry processes
Solution Approach 1:
The system performs preliminary calibration to determine optimized read voltages before actual data retrieval operations. This pre-determination of voltage values prevents decoding errors during normal operation, eliminating the need for retry processes and reducing data retrieval latency while maintaining multi-bit storage capacity
2Adaptability or versatility
If blind searching is used to find optimized read voltages, then adaptability to voltage shifts is improved, but processing time increases
Solution Approach 1:
The system performs a calibration process in advance to determine optimized read voltages for different threshold voltage distributions. By pre-calculating these voltage values and storing them in a lookup table, the system achieves adaptability to voltage shifts without performing time-consuming searches during actual data retrieval operations
Solution Approach 2:
Instead of searching for optimal voltages during data retrieval (forward approach), the system inverts the process by pre-determining voltages through calibration and storing them for later use. This reversal transforms a time-consuming search operation into a fast lookup operation
3Speed
If only hard bit data is read, then reading speed is improved, but error correction capability deteriorates
Solution Approach 1:
The system performs preliminary calibration to determine optimized read voltages that maximize both reading speed and error correction capability. By using these pre-determined voltages, the system achieves fast reading of hard bit data while maintaining strong error correction capability through accurate voltage selection
Solution Approach 2:
The system changes the read voltage parameter based on calibrated values to optimize the balance between reading speed and error correction capability. By adjusting the voltage to optimized values determined during calibration, the system achieves both fast reading and reliable error correction
Data Source
AI summary
A memory sub-system configured to read soft bit data by adjusting the read voltage applied to read hard bit data from memory cells. For example, in response to a read command identifying a group of memory cells, a memory device is to: read the group of memory cells using a first voltage to generate hard bit data indicating statuses of the memory cells subjected to the first voltage; change (e.g., through boosted modulation) the first voltage, currently being applied to the group of memory cells, to a second voltage and then to a third voltage; reading the group of memory cells at the second voltage and at the third voltage to generate soft bit data (e.g., via an exclusive or (XOR) of the results of reading the group of memory cells at the second voltage and at the third voltage).