Floating-Gate Semiconductor Structure Beyond Mask Scaling Limits
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Solution Overview
Problem
The miniaturization of semiconductor structures is hindered by limitations in manufacturing processes, particularly the design of patterned masks, which restrict further downscaling and performance improvements due to fixed distances between components, leading to unstable performance and dopant diffusion issues.
Innovation Solution
A semiconductor structure with a buried dummy structure is introduced, which shortens the distance between an active region and a substrate protrusion, and a method involving self-aligned core formation and etching to create these structures, allowing for uniform process loads and reduced dopant diffusion, thereby enhancing performance and reducing dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional mask design is used for patterning, then manufacturing process is simple, but further downscaling of semiconductor structure is limited
Solution Approach 1:
The patent segments the patterning process into multiple steps using self-aligned core structures. Instead of relying on a single mask design, the process divides the formation of recesses into sequential etching steps where each step creates a portion of the final pattern, enabling downscaling beyond conventional mask limitations
Solution Approach 2:
The patent introduces vertical dimensionality through self-aligned core structures that extend into the substrate. This vertical positioning enables precise lateral patterning in subsequent etching steps, effectively adding a dimensional degree of freedom that overcomes planar mask design constraints
2Manufacturing precision
If self-aligned core structures are formed, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The self-aligned core structures serve themselves as alignment references for subsequent etching steps. The core structures automatically define the positioning of recesses without requiring additional alignment marks or complex mask designs, achieving high precision while the system performs the alignment function autonomously
Solution Approach 2:
The core structures are formed in advance before the recess etching process. This preliminary formation establishes the geometric framework that guides all subsequent patterning steps, ensuring that positioning accuracy is predetermined rather than achieved through complex real-time alignment
Data Source
AI summary
A semiconductor structure includes a substrate, a dielectric structure, a floating gate, and a control gate. The substrate has a protrusion, a first recess, and a second recess, wherein the first recess and the second recess are on opposite sides of the protrusion. The dielectric structure extends from the first recess and the second recess to above a top surface of the protrusion. The floating gate is disposed over the substrate and adjoins a sidewall of the dielectric structure. The control gate is disposed over the floating gate and extends over a top surface of the dielectric structure to directly above the protrusion.