Separated Pass Transistor Layout for 3D NAND Selection Line Timing
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Solution Overview
Problem
As memory cell sizes decrease for higher integration in memory devices, the complexity of operation circuits and wiring structures increases, leading to larger chip sizes and non-uniform setup speeds of selection lines, which can cause timing margins to decrease and degrade data reliability in 3D NAND flash memory.
Innovation Solution
The formation of some pass transistors on a P-type semiconductor substrate, with some in a pocket P-type well area and others on a separate P-type substrate, allows for improved signal setup speeds of selection lines and reduces chip size by utilizing double-driven pass transistors to enhance operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of pass transistors connected to word lines increases to achieve larger memory capacities in 3D NAND flash memory, then storage capacity is improved, but chip size increases
Solution Approach 1:
The pass transistor circuit is divided into two separate circuits: a first pass transistor circuit disposed in a pocket P-type well area on the first P-type substrate, and a second pass transistor circuit disposed on a second P-type substrate. This segmentation allows the pass transistors to be distributed across different substrate areas, reducing the chip size required for a given storage capacity by utilizing both the main substrate and a separate substrate for the pass transistor circuits.
2Quantity of substance
If memory cell sizes decrease to provide higher integration, then integration density is improved, but complexity of operation circuits and wiring structures increases
Solution Approach 1:
By segmenting the pass transistor circuit into two separate circuits on different substrates, the wiring complexity is reduced as each circuit can be optimized independently. The first circuit handles specific word line driving functions while the second circuit handles other gate line driving functions, simplifying the overall wiring structure compared to a single integrated circuit.
Solution Approach 2:
The invention moves from a two-dimensional planar integration approach to a three-dimensional stacked approach by placing pass transistor circuits on both the first substrate and a separate second substrate. This vertical stacking in the third dimension increases integration density without proportionally increasing the planar chip area or wiring complexity.
3Quantity of substance
If the number of pass transistors increases to support more word lines, then memory capacity is improved, but setup speeds of selection lines become non-uniform, degrading data reliability
Solution Approach 1:
Dividing the pass transistor circuit into two separate circuits allows for independent optimization of signal driving capabilities. Each circuit can be designed to provide uniform setup speeds for its specific set of gate lines, preventing the non-uniform timing issues that arise when all pass transistors are concentrated in a single circuit. This segmentation ensures that selection lines maintain consistent setup speeds even as memory capacity increases through additional word lines.
Data Source
AI summary
A memory device includes a memory block including a plurality of cell strings coupled between a first P-type substrate and a plurality of memory blocks, a first pass transistor circuit including a plurality of first pass transistors configured to drive first gate lines from among the plurality of gate lines, and a second pass transistor circuit including a plurality of second pass transistors configured to drive second gate lines from among the plurality of gate lines. The plurality of cell strings are coupled with the plurality of gate lines including a string selection line, a plurality of word lines, and a ground selection line. The plurality of gate lines are stacked in a vertical direction. The first pass transistor circuit is disposed in a pocket P-type well area formed on the first P-type substrate. The second pass transistor circuit is disposed on a second P-type substrate.