Asymmetric Floating-Gate Layout for Uniform Memory Threshold Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving uniform threshold voltage and operational reliability due to non-uniform coupling ratios between floating gates, which affects the performance of non-volatile memory devices.
Innovation Solution
The design incorporates asymmetrically shaped floating gates and a wide gap between selection gates and active regions, along with complementary conductive type well regions, to ensure uniform threshold voltage and improved operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gates are arranged in a conventional symmetric configuration, then the device structure is simple, but the coupling ratio between floating gates becomes non-uniform, resulting in non-uniform threshold voltage and reduced operational reliability
Solution Approach 1:
The patent applies asymmetry by configuring floating gates with different shapes and sizes. Specifically, first and second floating gates have a first shape, while third and fourth floating gates have a second shape different from the first. This asymmetric arrangement compensates for non-uniform coupling ratios between adjacent floating gates, achieving uniform threshold voltage distribution across the memory device and improving operational reliability.
Solution Approach 2:
The patent implements local quality by making each floating gate have a specific shape tailored to its position in the array. The first and second floating gates have one shape configuration, while the third and fourth floating gates have a different shape configuration. This localized optimization ensures that each floating gate achieves uniform coupling with its neighbors, resolving the non-uniformity issue without requiring complete redesign of the entire device structure.
2Reliability
If a wide gap is introduced between selection gates and active regions, then interference is reduced and operational stability is improved, but the device area increases
Solution Approach 1:
The patent applies partial action by introducing gaps only in specific critical regions where interference occurs between selection gates and active regions. Rather than uniformly increasing spacing across the entire device, the gap is strategically placed to prevent interference while minimizing the overall area increase. This selective approach maintains operational stability without excessive area consumption.
3Manufacturing precision
If non-uniform coupling ratios exist between floating gates, then the device structure can be simpler, but the threshold voltage becomes non-uniform, affecting memory performance
Solution Approach 1:
The patent uses asymmetry in floating gate design to achieve uniform threshold voltage. By configuring first and second floating gates with a first shape and third and fourth floating gates with a second shape, the design compensates for position-dependent coupling ratio variations. This asymmetric shape configuration ensures that each floating gate achieves the desired coupling characteristics, resulting in uniform threshold voltage across the device.
Solution Approach 2:
The patent applies parameter changes by modifying the geometric parameters of floating gates (shape, size, orientation) to control coupling ratios. The first and second floating gates have different geometric parameters than the third and fourth floating gates. By adjusting these parameters locally, the patent achieves uniform threshold voltage distribution while managing device complexity.
Data Source
AI summary
A non-volatile memory device may include a substrate, a first floating gate, a second floating gate, a third floating gate and a fourth floating gate. The substrate may include an active region. The first to fourth floating gates may be formed on the substrate. The first to fourth floating gates may be radially arranged to be partially overlapped with the active region. The first floating gate and the third floating gate may face each other in a first direction. The first floating gate and the third floating gate may have asymmetrically planar shapes. The first floating gate and the second floating gate may face each other in a second direction substantially perpendicular to the first direction. The first floating gate and the second floating gate may have asymmetrically planar shapes. The third floating gate and the fourth floating gate may face each other in the second direction. The third floating gate and the fourth floating gate may have asymmetrically planar shapes. The fourth floating gate and the second floating gate may face each other in the first direction. The fourth floating gate and the second floating gate may have asymmetrically planar shapes.