Floating-Gate NOR Memory Cell Layout for Faster Programming
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Solution Overview
Problem
The efficiency of programming nonvolatile semiconductor memory cells is hindered by competing electric fields, which affect the direction and energy of electrons, leading to suboptimal programming and read current performance, resulting in design trade-offs.
Innovation Solution
The introduction of strategically placed indium implants throughout the substrate of the memory cell, combined with a specific architecture, enhances programming efficiency while maintaining high read current by optimizing threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell structure is adjusted to overcome competing electric fields and maintain optimal electron traveling direction during programming, then programming efficiency is improved, but threshold voltages of control gate are affected negatively which reduces read current
Solution Approach 1:
The patent introduces indium implants at specific locations (trench bottom, trench sidewall, and channel region) with different concentrations and depths to locally modify electric fields and threshold voltages. This localized doping approach allows optimization of electron injection efficiency at the floating gate interface while maintaining appropriate threshold voltages in the channel region for proper read current characteristics.
Solution Approach 2:
The patent modifies physical parameters including indium implant energy (50-150 keV), implant dose (1e14 to 1e16 atoms/cm²), and floating gate oxide thickness (50-150 nm) to optimize the balance between programming efficiency and read current. By adjusting these parameters, the electric field distribution and electron injection characteristics can be tuned independently from the threshold voltage characteristics.
2Productivity
If indium implants are added to improve programming efficiency, then device complexity increases, but manufacturing process becomes more challenging
Solution Approach 1:
The indium implantation process is segmented into multiple distinct steps: trench bottom implant, trench sidewall implant, and channel region implant. Each implant step targets a specific region with optimized parameters, allowing independent control of electric field modification in different areas. This segmentation enables complex functionality to be achieved through modular process steps rather than a single complex implant.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves programming speed and efficiency while ensuring minimal impact on read current performance, effectively addressing the trade-off between programming efficiency and read current sensitivity.
Implementation Method 1
The memory cell structure as described herein includes a plurality of indium implants that are strategically placed throughout the substrate of the memory cell
Data Source
AI summary
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a bit line region, a surface region apart from the bit line region in a lateral direction, and a trench region apart from the surface region in the lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate; an electrically conductive control gate; an electrically conductive word line; and a floating gate insulated from the substrate and the word line and comprising: a first tip substantially aligned with the sidewall portion of the trench region of the substrate; and a second tip self-aligned with an edge of the word line that is farthest from the second portion of the control gate.