Stairless 3D Memory Word Lines With Integrated Line-and-Via Contacts
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming stairless structures for vertical NAND strings, particularly in creating integrated line-and-via structures that effectively contact electrically conductive layers and extend through dielectric material portions without material junctions.
Innovation Solution
The semiconductor structure comprises an alternating stack of insulating and sacrificial material layers, with memory openings filled by electrically conductive layers that are laterally spaced by dielectric material portions, and an integrated line-and-via structure that contacts the conductive layers and extends through the dielectric material, forming a continuous volume with a metallic plate and via portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional stairless structures are formed using conventional methods, then the structure can be created, but material junctions are introduced that reduce structural integrity and operational efficiency
Solution Approach 1:
The patent merges the word line and contact into a single integrated line-and-via structure formed by continuous conformal deposition. This eliminates the material junction that would exist between separate word line and contact layers, creating a unified conductive path that improves structural integrity while reducing operational complexity.
Solution Approach 2:
The sacrificial material is deposited and patterned in advance to define the precise locations where the integrated line-and-via structure will form. This preliminary structuring enables the subsequent conformal deposition to automatically create the correct three-dimensional geometry without requiring additional alignment steps or material junctions.
2Reliability
If integrated line-and-via structures are formed without material junctions, then structural integrity is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The conformal deposition process automatically conforms to the underlying sacrificial material geometry, self-organizing to form the correct integrated line-and-via structure. This self-service mechanism eliminates the need for complex lithographic patterning and multiple deposition steps, simplifying manufacturing while achieving junction-free structures.
Solution Approach 2:
The sacrificial material acts as an intermediary template that guides the formation of the integrated line-and-via structure. By using this temporary mediator, the complex three-dimensional geometry can be formed through simple conformal deposition, after which the sacrificial material is removed to leave the final junction-free structure.
3Ease of manufacture
If conventional lithographic patterning is used to form word lines, then the process is straightforward, but stairless structures cannot be achieved
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional conformal deposition. By depositing materials conformally around the sacrificial material in three dimensions, the process naturally forms the stairless integrated line-and-via structure without requiring complex lithographic steps, achieving both ease of manufacture and the desired shape.
Solution Approach 2:
Instead of forming the integrated line-and-via structure directly through lithography and deposition, the patent inverts the approach by first depositing sacrificial material to define the negative space, then using conformal deposition to form the structure around it. This inversion simplifies the manufacturing process while achieving the stairless geometry.
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.