Memory Cell Programming Using Foggy-Fine Pass Loop Control
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Solution Overview
Problem
Existing memory devices face issues with interference between memory cells during program operations, leading to inefficiencies in execution time and power consumption.
Innovation Solution
The memory device employs a foggy program operation and a fine program operation, with a peripheral circuit that stores information about foggy program pass loops to determine a fine program pass condition, allowing for efficient determination of target program states without unnecessary verification steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional program operations are performed on memory cells, then data can be stored, but interference occurs between memory cells leading to increased execution time and power consumption
Solution Approach 1:
The patent divides the program operation into two distinct phases: foggy program operation and fine program operation. This segmentation allows each phase to target specific subsets of memory cells with optimized voltage patterns, reducing cross-interference while maintaining overall program efficiency. The foggy phase performs preliminary programming on a broader set of cells, while the fine phase refines specific cells that require additional programming, thereby minimizing unnecessary interference.
Solution Approach 2:
The patent applies different program voltages and verification strategies to different regions of memory cells based on their individual programming status. By identifying which specific memory cells have passed the foggy program operation and which require fine program operation, the system applies localized quality control - using stronger or extended programming only where needed rather than uniformly across all cells, thus reducing overall interference and power consumption.
2Manufacturing precision
If verification operations are performed to ensure proper programming, then programming accuracy is improved, but execution time and power consumption increase
Solution Approach 1:
The patent implements partial verification by performing verification operations only on memory cells that are suspected of incomplete programming. After the foggy program operation, the system identifies specific cells that may not have reached the target program state and applies fine program operation followed by verification only to those cells. This partial approach maintains high programming accuracy while significantly reducing the time and power overhead compared to verifying all cells.
Solution Approach 2:
The patent employs feedback mechanisms where verification results from the foggy program operation inform the fine program operation. Cells that fail verification are identified and targeted for additional programming in the fine phase, with subsequent verification to confirm success. This feedback-driven approach ensures high programming accuracy while minimizing unnecessary verification and re-programming operations, thereby reducing overall execution time and power consumption.
Data Source
AI summary
A memory device may include memory cells connected to a selected word line, and a peripheral circuit configured to store information regarding a foggy program pass loop in which a target program state is determined as foggy program pass during a foggy program operation on the selected word line, calculate a fine program pass loop based on the foggy program pass loop, and determine the target program state as fine program pass in the fine program pass loop of a fine program operation on the selected word line.