3D NOR Memory Word Line Selection for Lower Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional NOR memory arrays face challenges with high parasitic capacitance on global word lines, leading to increased latency and unintended disturb to unselected memory transistors.
Innovation Solution
The introduction of word line select transistors that selectively couple only a subset of local word lines to the global word line, reducing parasitic capacitance and minimizing disturbance to unselected memory transistors, while using ferroelectric memory transistors with a ferroelectric polarization layer as a gate dielectric to modulate threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all local word lines are coupled to the global word line, then complete memory array access is enabled, but parasitic capacitance increases and latency increases
Solution Approach 1:
The patent segments the coupling between global word lines and local word lines by introducing word line select transistors. Instead of directly coupling all local word lines to the global word line, the coupling is segmented into selective connections controlled by individual transistors, allowing only required local word lines to be activated during each operation.
Solution Approach 2:
The patent implements dynamic coupling where the connection between global and local word lines is not fixed but changes based on operational requirements. Word line select transistors enable or disable specific local word line connections dynamically, allowing the system to adapt the active memory strings according to the accessed data, thereby reducing unnecessary capacitive loading.
2Adaptability or versatility
If all local word lines are coupled to the global word line, then complete memory array access is enabled, but unintended disturb to unselected memory transistors occurs
Solution Approach 1:
The patent segments the electrical connection between global word lines and local word lines using word line select transistors. This segmentation isolates unselected memory strings from the global word line voltage swings, preventing capacitive coupling from causing unintended disturb to unselected memory transistors while still enabling complete array access when needed.
3Loss of time
If word line select transistors are introduced, then parasitic capacitance is reduced and latency is shortened, but device complexity increases
Solution Approach 1:
The patent introduces word line select transistors as intermediary devices between global word lines and local word lines. These intermediary transistors act as controlled switches that reduce parasitic capacitance by selectively connecting only required local word lines to the global word line, thereby reducing latency without completely sacrificing array access capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance, shortens the time to charge up the global word line, and lowers latency, enhancing the performance of the memory device by allowing individual addressing and access of memory transistors.
Implementation Method 1
using ferroelectric memory transistors with a ferroelectric polarization layer as a gate dielectric to modulate threshold voltage
Data Source
AI summary
A memory circuit includes an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting with local word line structures with global word lines arranged orthogonal to the array of NOR memory strings and aligned with a set of local word line structures provided across multiple stacks of NOR memory strings. The memory circuit includes a word line select transistor associated with each local word line structure to isolate each local word line structure from the associated global word line. The word line select transistor, when activated, selectively couples a selected local word line structure to the associated global word line. Remaining local word line structures associated with the same global word line remain disconnected and therefore not selected. In this manner, parasitic capacitance on the global word line is reduced and unintended disturb to other unselected memory transistors is also reduced.