Memory Fuse Circuit Layout With Power Gating for Low Leakage
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Solution Overview
Problem
Memory devices with metal fuses have large dimensions due to large transistors handling large currents, leading to significant leakage currents that deteriorate data access accuracy.
Innovation Solution
Implementing power-gate transistors and cascode-gate transistors in memory circuits, reducing the number of transistors and using them in parallel configurations to minimize leakage current and area, while maintaining program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large transistors are used to handle large currents for metal fuse operations, then the memory device can perform programming operations, but the device area becomes very large
Solution Approach 1:
The memory device is divided into multiple memory cells (e.g., 16 memory cells) that share common bit lines and word lines. Each memory cell contains a metal fuse element and associated transistors, but the bit lines and word lines are shared across multiple cells, reducing the overall device area while maintaining the capability to handle programming currents.
Solution Approach 2:
Multiple memory cells share common bit lines (BL0-BL3) and word lines (WL0-WL3), combining the interconnect structures to reduce redundancy. The power gate transistors are also configured to share control signals and structures, reducing the total transistor count and device area while maintaining current handling capability.
2Power
If large transistors are used to handle large currents for metal fuse operations, then the memory device can perform programming operations, but the leakage current becomes large which deteriorates data access accuracy
Solution Approach 1:
Power gate transistors (PGT0-PGT3) are introduced to dynamically control the power supply to memory cells during read operations. By turning off the power gate transistors during reads, the leakage current path is blocked, preventing leakage from affecting data accuracy. The transistors can be turned on during programming when high current is needed, and off during reads when low leakage is required.
Solution Approach 2:
The power gate transistors act as intermediary elements between the power supply and the memory cell transistors. They control the flow of current to the memory cells, enabling high current during programming and blocking current during reads, thus mediating between the conflicting requirements of current handling and leakage reduction.
3Power
If more transistors are used to improve current handling, then programming operations can be performed, but the device complexity increases
Solution Approach 1:
Multiple memory cells share common bit lines and word lines, reducing the total number of interconnect structures. Power gate transistors are shared across memory cells and controlled by common power gate word lines, reducing the total transistor count while maintaining the ability to handle programming currents across all cells.
Solution Approach 2:
The power gate transistors serve multiple functions: they enable current handling during programming operations, block leakage during read operations, and provide selective activation of memory cells. The shared bit lines and word lines serve multiple memory cells, reducing overall device complexity while maintaining full functionality.
Data Source
AI summary
A memory circuit includes a first word line extending in a first direction, a first bit line extending in a second direction different from the first direction, a second bit line extending in the second direction, a second word line extending in the second direction, a first transistor coupled to the first word line and a first node, a second transistor coupled to the first word line, and a second node, a first storage circuit to at least the first bit line, a second storage circuit coupled to at least the second bit line, and a third transistor coupled between the first node and the second node.