3D Memory Cell Layout With Shared Bit and Source Lines
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high density and small cell size, which are essential for advanced applications, as traditional two-dimensional circuits are limited in terms of memory cell density and efficiency.
Innovation Solution
The development of a three-dimensional (3D) memory architecture featuring a multi-level memory cell array with gate-all-around (GAA) transistor structures, where memory cells are arranged in multiple levels with interconnect structures providing bit and source lines, and word lines, allowing for increased density and efficiency through staggered cell positioning and shared interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional circuit architecture is used, then device structure is simple and manufacturing is easier, but memory cell density is limited and area cost is high
Solution Approach 1:
The patent transitions from traditional two-dimensional planar memory architecture to a three-dimensional stacked architecture. Multiple memory cell levels are stacked vertically along the Z-axis, with each level containing memory cells formed over corresponding bit lines and word lines. This vertical stacking enables significantly higher memory cell density within the same footprint area while maintaining manageable structural complexity through systematic layering and shared interconnect structures.
2Quantity of substance
If memory cell size is reduced to increase density, then memory density improves, but manufacturing precision requirements increase
Solution Approach 1:
The memory cell array is segmented into multiple discrete levels stacked vertically. Each level contains complete memory cells with distinct source regions, drain regions, channels, and gate electrodes. This segmentation allows each level to be formed using standardized processes while achieving high overall density through vertical multiplication of cells per unit area, reducing the precision burden on individual cell dimensions.
Solution Approach 2:
Interconnect structures serve multiple functions across different levels. Bit lines and word lines extend through multiple levels to provide electrical connections to memory cells at different stacked positions. This multi-functionality reduces the total number of interconnect structures needed while maintaining access to all memory cells, thereby reducing manufacturing complexity and precision requirements.
3Productivity
If three-dimensional stacked architecture is implemented, then memory cell density and efficiency increase, but device structure complexity increases
Solution Approach 1:
Multiple memory cell levels are merged into a single integrated three-dimensional structure. Memory cells at different levels share common bit lines, word lines, and control gate structures. This merging reduces the total number of separate interconnect structures required compared to implementing equivalent density using only planar two-dimensional cells, thereby managing structural complexity while achieving high density and efficiency.
Data Source
AI summary
Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.