Adaptive Memory State Partitioning for NAND Flash Program Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory cells near the edges of a string are susceptible to program disturb errors due to unintended programming, which existing techniques like self-boosting and local self-boosting fail to fully address, especially as word line spacing shrinks, leading to increased Gate Induced Drain Leakage (GIDL) and programming errors.
Innovation Solution
An adaptive memory-state partitioning scheme is implemented, where memory cells at the ends of a NAND string store fewer bits than the rest, allowing for a sufficient margin to mitigate errors, and additional cells may be added to maintain capacity, employing techniques like the 2-bit or 3-bit LM coding to manage data storage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells at the ends of NAND string store the same number of bits as other cells, then memory capacity is maximized, but program disturb errors increase due to susceptibility at edge cells
Solution Approach 1:
The patent applies different storage capacities to different locations within the memory system. Specifically, end memory cells (adjacent to select gates) are configured to store fewer bits (e.g., 1 bit) compared to intermediate memory cells (e.g., 2 bits). This local differentiation allows the vulnerable end cells to have sufficient noise margins while intermediate cells provide high capacity, resolving the contradiction between overall capacity and local reliability.
Solution Approach 2:
The memory system is segmented into distinct regions: end memory cells and intermediate memory cells. Each segment serves a different function - end cells provide error-resistant boundary conditions while intermediate cells provide bulk storage capacity. This segmentation allows the system to optimize for both reliability at vulnerable points and capacity in the bulk.
2Quantity of substance
If word line spacing is reduced to increase memory density, then memory capacity increases, but Gate Induced Drain Leakage (GIDL) increases causing more programming errors
Solution Approach 1:
The patent applies preliminary protective measures to end memory cells that are most susceptible to GIDL effects. By configuring these cells to store fewer bits and using them primarily for error-resistant functions, the system preemptively protects against the harmful effects of GIDL that become more severe with reduced word line spacing.
Solution Approach 2:
Different error protection strategies are applied locally - end memory cells use simplified error-resistant encoding while intermediate memory cells can use more aggressive high-density encoding. This allows the system to tolerate higher GIDL rates in dense configurations by concentrating error protection where it is most needed.
3Reliability
If adaptive memory-state partitioning is implemented to reduce errors, then reliability improves, but device complexity increases due to different storage schemes
Solution Approach 1:
The memory system is divided into end regions and intermediate regions with different storage configurations. This segmentation creates manageable complexity by limiting the number of different storage schemes needed - only two distinct configurations are required (end cell mode and intermediate cell mode) rather than completely arbitrary variations.
Solution Approach 2:
The patent merges the error protection function with the storage function by using the same physical memory cells for both purposes. End memory cells simultaneously provide error-resistant boundary conditions and contribute to overall capacity, eliminating the need for separate protection circuits or structures.
Data Source
AI summary
A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.