3D Memory Channel With Resonant Tunneling Barrier for Charge Retention
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high mobility channels and efficient resonant tunneling barriers, leading to limitations in storage density and operational efficiency.
Innovation Solution
A memory device is designed with an alternating stack of insulating and control gate layers, featuring a memory opening filled with a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer, which enhances charge storage and mobility through optimized bandgap configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional barrier structures are used in three-dimensional memory devices, then manufacturing is simpler, but charge retention and storage density are limited
Solution Approach 1:
The barrier structure is segmented into multiple distinct layers: a first barrier layer adjacent to the channel, a resonant tunneling barrier layer in the middle, and a second barrier layer adjacent to the charge storage layer. This segmentation allows each layer to perform its specific function optimally, improving charge retention while maintaining manufacturability through modular design
Solution Approach 2:
The barrier structure uses composite materials with different bandgap characteristics - the first and second barrier layers have wider bandgaps than the channel material, while the resonant tunneling barrier layer has specific thickness and material properties (such as AlGaAs with 2-3 nm thickness) to enable quantum tunneling effects. This composite approach enhances charge retention through optimized band alignment
2Quantity of substance
If higher storage density is achieved through vertical stacking, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The resonant tunneling barrier layer is designed with specific thickness parameters (2-3 nm) and material composition (such as AlGaAs) to exploit quantum mechanical tunneling effects. By precisely controlling these parameters, the device achieves high storage density through vertical stacking while the resonant tunneling mechanism provides natural sensitivity to thickness variations, reducing the impact of manufacturing tolerances
Solution Approach 2:
The invention transitions from planar memory structures to three-dimensional vertical stacking, with multiple barrier layers and charge storage regions arranged vertically. This dimensional change increases storage density by utilizing the vertical dimension, and the resonant tunneling barrier provides a mechanism that is inherently sensitive to the nanoscale thickness control achievable with modern semiconductor fabrication
3Use of energy by moving object
If operational voltage is reduced for low-power operation, then energy consumption decreases, but charge injection efficiency worsens
Solution Approach 1:
The invention replaces conventional charge injection mechanisms that rely on high electric fields with quantum mechanical resonant tunneling. The resonant tunneling barrier layer enables electrons to tunnel through the barrier at lower voltages by exploiting quantum mechanical effects, thereby reducing power consumption while maintaining charge injection efficiency that would otherwise require higher operational voltages
Solution Approach 2:
The resonant tunneling barrier exploits quantum phase effects where electrons transition between different quantum states. By tuning the barrier thickness and material composition to specific values, the device enables efficient charge injection through resonant tunneling at reduced voltages, achieving low-power operation without sacrificing injection efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves charge retention, reduces operational voltages, and increases storage density, enabling low-power, high-efficiency programming and erase operations while maintaining excellent read performance.
Implementation Method 1
The memory film contains a resonant tunneling barrier stack
Implementation Method 2
an alternating stack of insulating layers and control gate layers
Data Source
AI summary
A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer.