3D Memory Cell Structure With Submicron Vias and Thermal Layer Separation
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Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges in achieving high-density connections between layers due to misalignment issues and the degradation of wiring layers when constructing transistors at high temperatures, leading to limited connectivity and performance bottlenecks.
Innovation Solution
The development of a 3D semiconductor device architecture that includes a first single crystal layer with transistors and metal interconnects, a second level with memory cells, and a third level with polysilicon channels, where the metal layers are designed to have twice the thickness of the interconnects, and a conductive path with vias less than 1 micron in diameter, allowing for improved connectivity and heat management without damaging underlying metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed at high temperatures (>700°C) to improve transistor performance, then transistor density and performance improve, but the underlying wiring layers (constructed at <400°C) are damaged
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking, allowing transistor layers to be positioned above wiring layers in the vertical dimension. This enables high-temperature transistor processing without exposing the wiring layers to damaging temperatures, as the wiring layers remain in the lower temperature zone while transistors are formed in upper layers.
Solution Approach 2:
The patent divides the semiconductor structure into multiple stacked layers with different temperature zones. Lower layers (wiring layers) are processed at lower temperatures while upper layers (transistor layers) are processed at higher temperatures, allowing each layer to be optimized independently without mutual interference.
2Speed
If wafer bonding is used to stack transistor layers to reduce wire lengths, then wiring delay decreases, but misalignment between layers occurs due to wafer bowing and thermal expansion
Solution Approach 1:
The patent performs preliminary alignment mark formation and bonding interface preparation before the actual wafer bonding process. Alignment marks are created on both wafers beforehand, allowing precise registration during bonding despite thermal expansion and bowing effects that occur during processing.
Solution Approach 2:
The patent uses alignment marks as intermediary reference features between the two wafers. These marks serve as mediators that enable precise alignment during bonding by providing fixed reference points that compensate for thermal expansion and mechanical bowing of the wafers.
3Productivity
If Through-Silicon Vias (TSVs) are used to create connections between stacked wafers, then vertical connectivity is achieved, but the contact size must be large which limits connection density
Solution Approach 1:
The patent changes the dimensional parameters of the contact structures by forming small-diameter vias (less than 1 micron) through the transistor layers to reach the wiring layers. This parameter change enables high-density vertical connections without requiring large contact areas, thereby increasing connection density while maintaining effective electrical pathways.
Data Source
AI summary
3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.