3D NOR Memory Word Line Staggering to Reduce Cell Disturb
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Solution Overview
Problem
In high-density three-dimensional NOR-type memory arrays, memory cells are prone to interference due to close proximity, leading to disturbs during program, erase, or read operations, which compromises memory cell density and reliability, especially in multilevel cell modes.
Innovation Solution
A staggered memory cell architecture is implemented, where memory cells on opposite sides of a shared bit line are offset relative to each other, increasing the distance between them and connecting to global word lines either underneath or above the memory structure, thereby reducing parasitic interference without sacrificing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are placed in close proximity to increase density, then memory cell density is improved, but cell-to-cell interference increases causing disturbs during operations
Solution Approach 1:
The patent applies asymmetry by staggering word lines in alternating patterns (e.g., even word lines at one position, odd word lines at another position) rather than using uniform alignment. This asymmetric arrangement increases the distance between memory cells on adjacent bit lines while maintaining high density, thereby reducing cell-to-cell interference and improving operation reliability.
Solution Approach 2:
The patent introduces a new dimensional arrangement by staggering word lines across multiple levels or positions in the vertical or lateral dimension. Instead of simple planar alignment, word lines are offset in the third dimension (height or depth), creating a three-dimensional staggered architecture that reduces interference while preserving density.
2Reliability
If memory cells are separated by larger distance to reduce interference, then cell-to-cell interference is reduced, but memory cell density decreases
Solution Approach 1:
The patent utilizes three-dimensional space by staggering word lines at different vertical positions or depths. This allows memory cells to be separated in the vertical dimension while maintaining close horizontal spacing, thus reducing interference without sacrificing planar density.
Solution Approach 2:
The asymmetric staggering pattern creates non-uniform spacing where critical interfering cells are positioned farther apart, while non-critical cells remain close. This selective asymmetric arrangement reduces interference for operations that matter most while maintaining overall high density.
3Ease of manufacture
If uniform word line alignment is used to simplify manufacturing, then manufacturing complexity is reduced, but cell-to-cell disturb increases
Solution Approach 1:
The patent segments the word line array into groups (even word lines and odd word lines) that are staggered relative to each other. This segmentation into distinct groups with different positions simplifies the manufacturing process by allowing independent patterning and alignment of each group, while the staggered arrangement reduces cell-to-cell disturb.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces cell-to-cell interference, maintaining high memory cell density while enabling viable multilevel cell operations by increasing the distance between nearest memory cells and minimizing threshold voltage shifts.
Implementation Method 1
reducing parasitic interference without sacrificing density
Data Source
AI summary
A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.