Flash Memory Charge Pump Stages That Prevent Last-Stage Voltage Droop
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Solution Overview
Problem
Prior art charge pumps experience a deficiency in the last boost stage where the voltage actually decreases, leading to inefficient charge transfer and lower output voltage due to the shut-off of the pass gate transistor, especially at low power supply voltages and high threshold voltages.
Innovation Solution
The proposed solution involves modifying the boost stage design by increasing the amplitude of clock signals using a clock doubling circuit and incorporating local feed-forward or feed-backward precharge circuits with diodes or PMOS transistors to ensure the pass gate remains on and maintain the output voltage at least as high as the input voltage, preventing voltage drooping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional boost stage design is used in the last stage of a charge pump, then the circuit complexity is low, but the output voltage decreases and charge transfer efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-charging the gate of the pass gate transistor through a dedicated pre-charge path before the main charge transfer operation. This ensures the pass gate is already in a conductive state ready for efficient charge transfer, preventing the voltage droop that occurs in conventional designs where the gate charges simultaneously with or after the main operation begins.
Solution Approach 2:
The patent introduces an intermediary element - a separate pre-charge transistor or circuit path - that mediates the charging of the pass gate. This intermediary component ensures the gate reaches the required voltage level independently and before the main charge transfer, resolving the contradiction by adding a specialized component rather than modifying the core charge pump operation.
2Productivity
If the clock signal amplitude is increased to maintain pass gate conduction, then charge transfer efficiency improves, but the energy consumption increases
Solution Approach 1:
The patent uses preliminary action by pre-charging the pass gate through a dedicated low-power pre-charge path that operates independently of the main clock signal. This allows the gate to reach the necessary voltage level using minimal energy before the main charge transfer operation, avoiding the need to continuously drive the gate with high-amplitude clock signals that would consume excessive energy.
Solution Approach 2:
The patent segments the gate charging operation into two distinct phases: a low-power pre-charge phase using a dedicated pre-charge path, and the main charge transfer phase. This segmentation allows each phase to be optimized independently - the pre-charge phase for minimal energy consumption and the main phase for efficient charge transfer - resolving the contradiction between efficiency and energy usage.
3Reliability
If the pass gate transistor is kept on during low supply voltages, then output voltage is maintained, but the threshold voltage effects worsen
Solution Approach 1:
The patent applies preliminary action by pre-charging the pass gate to a voltage level that compensates for threshold voltage drops before the main charge transfer operation. This pre-charge ensures that even when supply voltages are low and threshold effects are significant, the gate maintains sufficient overdrive voltage to remain conductive and transfer charge effectively, stabilizing the output voltage despite adverse threshold effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the efficiency of charge transfer and maintains the output voltage of the last stage at least as high as the previous stage, even at low VDD supply or high threshold voltages, effectively addressing the inefficiencies in prior art charge pumps.
Implementation Method 1
The clock signal is applied to a capacitor to increase the potential of the gate of the N channel MOS transistor
Implementation Method 2
a P channel MOS transistor is connected between a gate and a drain of switching N channel MOS transistor. The P channel MOS transistor is controlled to be on/off by a switching circuit
Implementation Method 3
A parallel-coupled MOS pair (M2, M3) is coupled between drain (input node) and source (output node) of the charge transfer device, in which M3 is configured as a diode. The t1 phi 1 positive transient is AC-coupled to M1's drain, and a smaller fraction of the transient is coupled to M1's gate, precharging M1, which begins to turn-on
Implementation Method 4
incorporating local feed-forward or feed-backward precharge circuits with diodes or PMOS transistors to ensure the pass gate remains on and maintain the output voltage at least as high as the input voltage
Data Source
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AI summary
Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.