3D Vertical Memory Cell Structure for Efficient Erase Operations
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving a three-dimensional memory structure with efficient data storage and retrieval, particularly in the design of the source layer, gate layer, and stacked body configuration, which affects the performance and reliability of memory cells.
Innovation Solution
The semiconductor device incorporates a source layer with a semiconductor layer including an impurity, a stacked body with insulator-interposed electrode layers, a gate layer thicker than the electrode layers, and a semiconductor body extending through the stacked body and gate layer, with a charge storage portion between the semiconductor body and electrode layers, enabling a vertical transistor structure for nonvolatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional memory structure with side wall contact is used, then data storage efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The memory structure is segmented into distinct functional layers: source layer, gate layer, stacked body with electrode layers, and charge storage portions. This segmentation allows each layer to be optimized and manufactured independently, reducing the overall manufacturing precision requirements while maintaining data storage efficiency.
Solution Approach 2:
The invention transitions from planar memory structures to three-dimensional vertical structures with electrode layers stacked in the vertical dimension. This dimensional change increases storage density without requiring proportionally higher manufacturing precision, as the stack alignment can be achieved through standard lithographic processes.
2Reliability
If the gate layer is made thicker than electrode layers, then channel induction is improved, but device complexity increases
Solution Approach 1:
Different layer thicknesses are applied locally to different functional regions: the gate layer is made thicker than individual electrode layers specifically at regions requiring strong channel induction, while other layers maintain their standard thicknesses. This localized thickness variation optimizes channel induction without uniformly increasing device complexity.
3Productivity
If impurity is included in the semiconductor layer, then erase operation efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
Impurities are pre-diffused into the semiconductor layer during the manufacturing process before device operation. This preliminary action ensures that the semiconductor layer has the required impurity concentration for efficient erase operations, eliminating the need for complex in-operation impurity management while achieving high erase efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient electrical erasure and programming of data, retaining memory content even when power is off, with improved channel induction and erase operations due to the impurity diffusion and thick gate layer functionality.
Implementation Method 1
improved channel induction and erase operations due to the impurity diffusion
Data Source
AI summary
According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.