3D NOR Flash Memory Cell Structure for Higher Integration
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Solution Overview
Problem
Current NOR flash memory devices face challenges in achieving higher integration and larger capacity while maintaining efficient data storage operations, particularly in the design and manufacturing of memory cell arrays.
Innovation Solution
The proposed memory device incorporates a stacked interconnect structure with semiconductor and conductive layers, charge storage films, and insulating films, allowing for the vertical stacking of memory cell transistors, which enhances integration and capacity without increasing chip size, and utilizes a manufacturing process similar to NAND flash memory techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is implemented, then storage capacity and integration are increased, but device complexity increases
Solution Approach 1:
The patent transitions from a planar two-dimensional memory structure to a three-dimensional stacked structure by adding vertical layers (first semiconductor layer, first conductive layer, second semiconductor layer, second conductive layer with memory films between them). This dimensional change enables increased storage capacity while maintaining a compact footprint, directly resolving the contradiction between storage capacity and device complexity.
2Productivity
If a stacked interconnect structure is used, then integration is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into distinct segmented layers (first semiconductor layer, first conductive layer, second semiconductor layer, second conductive layer) with memory films positioned between specific layers. This segmentation allows each layer to be manufactured and controlled independently, reducing the cumulative precision requirements compared to a monolithic structure, thereby enabling enhanced integration while managing manufacturing precision challenges.
Data Source
AI summary
According to one embodiment, a memory device includes: a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a second conductive layer that are arranged in this order in a first direction, spaced apart from each other; a first semiconductor film extending in the first direction, being in contact with the first semiconductor layer and the second semiconductor layer, and intersecting the first conductive layer and the second conductive layer; a first memory film provided between the first conductive layer and the first semiconductor film; and a second memory film provided between the second conductive layer and the first semiconductor film.