Parallel Memory ATPG Using Subset Enable Logic
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Solution Overview
Problem
Current testing methods for memory circuits, particularly those with complex architectures and multiple physical memories, face challenges in efficiently testing timing critical paths due to large numbers of control points and lengthy test times, especially when using RAM sequential ATPG and BIST techniques.
Innovation Solution
A method and circuit design that enables multiple parallel memory units to be tested simultaneously by dividing them into subsets, allowing simultaneous enabling and testing through logic gate arrays and flip-flops, reducing test time and semiconductor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple physical memories are tested using traditional sequential ATPG methods, then testing coverage is achieved, but test time becomes excessively long
Solution Approach 1:
The memory units are divided into multiple subsets, with each subset being tested by a dedicated test controller in parallel. This segmentation allows simultaneous testing of multiple memory subsets, reducing overall test time while maintaining comprehensive coverage of all memory units.
Solution Approach 2:
Multiple test controllers are combined to operate simultaneously on different memory subsets. The test system merges parallel testing capabilities across multiple controllers, enabling concurrent execution of test patterns on different memory portions without interfering with each other.
2Loss of time
If multiple memory units are tested in parallel using traditional methods, then test time is reduced, but control point complexity increases significantly
Solution Approach 1:
The control functionality is segmented and distributed across multiple independent test controllers, each managing a specific subset of memory units. This distribution reduces the control point complexity at any single controller while enabling parallel operation to reduce test time.
Solution Approach 2:
Each test controller is designed as a universal unit capable of independently controlling and testing its assigned memory subset. This multi-functional design allows each controller to handle all necessary test operations for its subset, reducing overall system complexity through standardization.
3Productivity
If more memory units are enabled simultaneously for testing, then parallelism and test efficiency improve, but power consumption and grid complexity increase
Solution Approach 1:
Memory units are segmented into subsets that can be independently enabled and tested. This allows the system to enable only the necessary number of memory units in parallel based on testing requirements, optimizing power consumption while maintaining test efficiency.
Solution Approach 2:
The system dynamically controls the enabling of memory units based on testing progress and requirements. Test controllers can selectively enable or disable specific memory subsets during the testing process, allowing flexible power management that adapts to current testing needs.
Data Source
AI summary
Systems and methods may perform sequential automatic test pattern generation (ATPG) on parallel memory units. A first array of logic gates may output enable signals to cause multiple memory units to be enabled in parallel. Test pattern generation and test control logic may perform forward path testing, backward path testing, and any other appropriate testing on the enabled memory units. The systems and methods may then move on to another group of memory units, which are enabled in parallel and tested in parallel.