Hybrid QLC Data Routing for Reduced RAM Footprint
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Solution Overview
Problem
The existing multi-level cell (MLC) programming process in non-volatile memory requires large RAM buffers to store data temporarily during the Foggy-Fine programming steps, leading to increased controller costs and memory requirements, especially as the number of memory planes and strings increases.
Innovation Solution
A hybrid QLC data routing scheme is implemented, where a mix of incoming host data and previously-written data is routed to QLC blocks, reducing the RAM requirements and allowing for hybrid routing and folding on different dies, thereby reducing the need for large write buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a traditional Foggy-Fine programming process is used for MLC/QLC memory, then programming precision is improved, but RAM buffer requirements increase
Solution Approach 1:
The patent segments the programming process into distinct phases (Foggy programming and Fine programming) and processes different memory planes in sequence rather than simultaneously. This allows the system to reuse the same RAM buffer for different planes at different times, reducing the total buffer capacity needed while maintaining programming precision through staged processing
Solution Approach 2:
The patent implements a nested structure where Fine programming operations are embedded within the overall Foggy-Fine programming sequence. The system completes Foggy programming for a plane, then performs Fine programming for that same plane before moving to the next plane, allowing efficient reuse of buffer resources across nested operational levels
2Productivity
If the number of memory planes and strings is increased, then memory capacity is improved, but RAM buffer requirements increase
Solution Approach 1:
The patent divides the memory system into multiple planes and strings that are processed in sequential batches. By segmenting the programming operations across time rather than requiring simultaneous buffering for all planes, the system achieves high memory capacity without proportionally increasing RAM buffer requirements
Solution Approach 2:
The patent employs periodic action by cycling through different planes in a structured sequence (e.g., Plane 0 Foggy, Plane 1 Foggy, Plane 0 Fine, Plane 1 Fine). This periodic pattern allows the same buffer resources to be reused across multiple cycles, enabling support for multiple planes and strings without linearly increasing buffer capacity
3Quantity of substance
If a hybrid QLC routing scheme is implemented, then RAM requirements are reduced, but device complexity increases
Solution Approach 1:
The patent implements dynamic routing that adapts based on the programming phase and plane being processed. The system dynamically selects which planes to program in each cycle and adjusts the routing accordingly, allowing flexible resource utilization that reduces RAM requirements while managing complexity through adaptive control rather than fixed complex hardware
Solution Approach 2:
The patent introduces a controller as an intermediary that manages the hybrid QLC routing logic. This mediator coordinates the complex interactions between different planes, strings, and programming phases, abstracting the complexity away from the underlying hardware and enabling reduced RAM requirements through intelligent resource management
Data Source
AI summary
A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.