Fringeless Transistor Gate Segmentation for Dense Multi-Voltage FETs

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Solution Overview

Problem

Developing semiconductor structures and methods to achieve high device density for field effect transistors operating at different operating voltages is challenging, particularly in memory device peripheral circuitry.

Innovation Solution

The semiconductor structure comprises multiple field effect transistors with specific gate electrode configurations and trench isolation structures, including a combination of semiconductor and metallic gate electrodes, and shared source/drain regions, to optimize device density and voltage operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple field effect transistors with different operating voltages are integrated to increase device density, then the device density is improved, but the circuit complexity and manufacturing difficulty increase due to requiring different gate electrode configurations

Engineering Contradiction:
Improvedevice densityVSAvoidgate electrode configuration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The gate electrode is segmented into two distinct portions: a first gate electrode portion for a first field effect transistor operating at a first voltage, and a second gate electrode portion for a second field effect transistor operating at a second voltage. This segmentation allows each transistor to be optimized for its specific operating voltage while sharing a common structure, thereby increasing device density without proportionally increasing overall complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A single gate electrode structure serves multiple functions by controlling two different field effect transistors with different operating voltages. The gate electrode acts as both the first gate electrode for the first transistor and the second gate electrode for the second transistor, reducing the total number of separate gate structures needed and improving device density

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple field effect transistors with different operating voltages are integrated to increase device density, then the device density is improved, but the manufacturing precision requirements increase due to different voltage operation needs

Engineering Contradiction:
Improvedevice densityVSAvoidvoltage operation precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Different portions of the gate electrode are designed with different characteristics: the first gate electrode portion is configured for the first operating voltage with its specific material composition and dimensions, while the second gate electrode portion is configured for the second operating voltage with its own material composition and dimensions. This local differentiation allows each transistor to achieve precise voltage operation while maintaining high device density through integrated sharing of the gate structure

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240147730A1Transistor circuits including fringeless transistors and method of making the same
Publication Date: 2024.05.02 SANDISK TECHNOLOGIES LLC
  • US20240147730A1 patent drawing
  • US20240147730A1 patent drawing
  • US20240147730A1 patent drawing

AI summary

A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.