Bridge Chip Command Duplication for Parallel Memory Transfer
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Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in data transfer between a memory controller and multiple memory chips due to limitations in the bridge chip's ability to manage and synchronize commands across multiple channels, leading to suboptimal performance and increased processing times.
Innovation Solution
The semiconductor memory device employs a bridge chip that duplicates and synchronizes command sequences across multiple channels, using logical unit numbers (LUNs) to identify and manage memory chips in groups, allowing simultaneous data transfer operations, thereby optimizing data-in, page read, and data-out processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bridge chip is used to manage data transfer between memory controller and multiple memory chips, then data transfer capability is improved, but processing time increases due to sequential command management
Solution Approach 1:
The command sequence is segmented and distributed to multiple channels simultaneously. The bridge chip divides the single command sequence into multiple parallel command sequences, each sent to different memory chips through separate channels, enabling concurrent data transfer operations and reducing total processing time.
Solution Approach 2:
Command sequences are prepared and duplicated in advance before actual data transfer begins. The bridge chip pre-processes the command sequence by creating multiple copies with appropriate channel identifiers, so that when data transfer starts, multiple channels can execute simultaneously without sequential delays.
2Device complexity
If command sequences are sent sequentially through a single channel, then command management is simplified, but data transfer speed decreases
Solution Approach 1:
The original command sequence is copied multiple times, with each copy modified to include the appropriate channel identifier. This allows the bridge chip to send identical command sequences through multiple channels simultaneously, dramatically increasing data transfer speed while maintaining simple command management logic through automated duplication.
Solution Approach 2:
The bridge chip is designed with multi-functional capability to handle multiple channels simultaneously. It can receive a single command sequence and automatically distribute it across multiple channels, making the system capable of both simplified command management and high-speed parallel data transfer.
3Productivity
If multiple channels are used for simultaneous data transfer, then transfer efficiency is improved, but synchronization complexity increases
Solution Approach 1:
The bridge chip acts as an intermediary that centralizes control over multiple channels. It receives the original command sequence, creates synchronized copies for each channel, and manages the timing and coordination of parallel transmissions, thereby improving transfer efficiency while containing synchronization complexity within the bridge chip itself.
Solution Approach 2:
The system implements feedback mechanisms where the bridge chip monitors the status of multiple channels and adjusts command sequencing accordingly. This feedback control ensures proper synchronization of parallel data transfers while maintaining high transfer efficiency, as the bridge chip can coordinate channel operations based on real-time status information.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a first chip, a second chip, and a third chip. The third chip is connected to the first chip via a first channel and connected to the second chip via a second channel. Upon receiving a first command sequence for data transfer from a first device, the third chip transfers a second command sequence for the data transfer to the first chip via the first channel and transfers a third command sequence for the data transfer to the second chip via the second channel. The first address includes a chip identification number of a value indicating the first chip. The second command sequence includes the first address. The third command sequence includes a second address obtained by replacing the value of the chip identification number in the first address indicating the first chip to a value indicating the second chip.