Double-Sense Memory Verify Charging to Reduce Data Line Decay
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Solution Overview
Problem
Conventional memory devices suffer from performance degradation due to additional coupling capacitance during precharging in write verify operations, leading to prolonged charge decay on data lines.
Innovation Solution
Implementing a memory device with a control unit that enables a double sense operation in the same write verify stage, allowing concurrent verification of two target threshold voltage levels by controlling charge distribution on data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If precharging is performed in conventional verify operations, then multiple target threshold voltage levels can be concurrently verified, but additional coupling capacitance is added between data lines which prolongs charge decay time
Solution Approach 1:
The patent divides the data line precharging process into two distinct phases: an initial charging phase where first data lines are charged to a first voltage level, and a subsequent charging phase where the same data lines are charged to a second voltage level. This segmentation allows optimized charging at different stages, reducing overall charge decay time while maintaining the ability to verify multiple threshold voltage levels concurrently.
Solution Approach 2:
The patent applies preliminary action by performing the initial charging phase before the subsequent charging phase. During the initial charging phase, data lines are precharged to the first voltage level, which prepares the lines in advance for the verify operation. This preliminary precharging reduces the time required for charge decay during the actual verify operation, thereby improving overall productivity without sacrificing verification accuracy.
2Ease of operation
If data lines are precharged to verify multiple threshold voltage levels, then write verify stage can be completed in one operation, but charge on data lines takes longer to decrease
Solution Approach 1:
The patent implements dynamic charging strategies by adjusting the voltage level applied to data lines based on the verification stage. During the initial charging phase, a first voltage level is applied, and during the subsequent charging phase, a second voltage level is applied. This dynamic adjustment optimizes the charging process to reduce charge persistence duration while maintaining the simplicity of verifying multiple threshold voltage levels in a single write verify stage operation.
Solution Approach 2:
The patent employs periodic action by structuring the precharging process into distinct time periods: an initial charging phase followed by a subsequent charging phase. Each phase has specific voltage levels and timing characteristics. This periodic structure allows the system to maintain ease of operation for concurrent verification while controlling the duration that charge persists on data lines, as each phase is time-bound and optimized for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for the write verify stage, enhancing the performance and efficiency of memory operations by minimizing charge decay on data lines.
Implementation Method 1
additional coupling capacitance between data lines. The additional coupling capacitance would take longer for the charge on the data lines to decrease.
Data Source
AI summary
Some embodiments include apparatuses and methods using first and second data lines coupled to respective first and second memory cell strings; an access line shared by first and second memory cells of the first and second memory cell strings, respectively; and a control unit including circuitry to perform operations including charging the first data line to a first voltage during a first time interval of an operation performed on first and second memory cells; holding the second data line at a second voltage during the first time interval; charging the first data line to a third voltage during a second time interval of the operation; charging the second data line to a fourth voltage during the second time interval; and determining, during the second time interval of the operation, whether the first memory cell reaches a first threshold voltage and whether the second memory cell reaches a second threshold voltage.