RAIN Parity Layout for Read Distress in NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems face challenges in correcting multiple errors simultaneously due to program disturb and read distress errors, which can occur in adjacent word lines and sub-blocks, leading to data integrity issues.
Innovation Solution
Implementing a redundant array of independent NAND (RAIN) parity scheme that generates and stores parity information for consecutive word lines, allowing simultaneous correction of errors across sub-blocks and word lines by calculating parity pages through XOR operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used, then single errors can be corrected, but multiple simultaneous errors in adjacent word lines and sub-blocks cannot be corrected
Solution Approach 1:
The patent segments the memory system into multiple independent NAND die, each with its own parity pages. This segmentation allows errors in one die to be corrected independently without affecting others, enabling correction of multiple simultaneous errors across different die while maintaining manageable complexity in each individual die.
Solution Approach 2:
The patent introduces a new dimension of error protection by storing parity information across multiple die rather than within a single die. This cross-die parity approach adds a spatial dimension to error correction, allowing the system to correct multiple errors that would be impossible to handle with traditional single-die methods.
2Reliability
If parity information is stored for every word line, then read distress errors can be corrected, but storage overhead and system complexity increase
Solution Approach 1:
The parity pages stored in each NAND die serve multiple functions: they correct program disturb errors within the same die, correct read distress errors from adjacent word lines, and provide recovery capability for multiple simultaneous errors. This multi-functionality reduces the need for separate error correction mechanisms, thereby reducing overall system complexity.
Solution Approach 2:
The patent changes the organizational parameters of parity storage by distributing parity pages across multiple die rather than concentrating them in one location. Each die contains parity information for its own data pages, creating a decentralized parity structure that reduces access complexity and improves error correction efficiency.
3Reliability
If conventional parity schemes are used, then program disturb errors can be corrected, but multiple simultaneous errors across sub-blocks cannot be recovered
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing parity pages for each set of consecutive word lines before errors occur. These parity pages are stored in dedicated parity word line groups within each NAND die, ready to immediately correct program disturb errors and multiple simultaneous errors without requiring complex real-time calculations.
Solution Approach 2:
The patent creates redundant copies of data through parity pages stored in separate word line groups within each die. These parity copies can be used to reconstruct original data when errors occur, providing robust recovery capability for multiple simultaneous errors without requiring external intervention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RAIN scheme effectively corrects multiple errors in memory systems, enhancing data integrity and performance by reducing errors and improving response times, power consumption, and security in electronic devices.
Implementation Method 1
calculate a set of parity pages for the set of consecutive word lines by combining a set of data pages associated with the set of consecutive word lines
Data Source
AI summary
Methods, systems, and devices for a parity scheme for read distress protection in a memory system are described. The parity scheme described herein may protect data against read distress errors. A set of consecutive word lines in a memory system may include one or more word line groups and one or more sub-block groups. The memory system may store, in a word line group of the set of consecutive word lines, parity information for the set of consecutive word lines. Each parity page may be a combination of one page of data per sub-block group and per word line group of the set of consecutive word lines. For example, each sub-block group and each word line group may contain N pages, where each of the N pages may correspond to a unique parity page to provide for recovery from errors caused by both read and program distresses.