Memory Cell Write Control Using Adjustable Row and Column Switches
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Solution Overview
Problem
Existing semiconductor devices struggle to efficiently store data at multiple levels without process changes, limiting their data storage capacity.
Innovation Solution
A semiconductor device with a configuration that includes column and row switches and memory cells, where the turn-on degree of transistors is adjusted by varying the voltage levels of address signals to control the direction and amount of current flow during write operations, allowing data to be stored at multiple levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor devices are used, then the device structure remains simple, but the data storage capacity is limited and cannot efficiently store data at multiple levels
Solution Approach 1:
The patent applies dynamics by making the switch transistor characteristics adjustable through voltage control. The column and row switches change their turn-on degrees dynamically based on applied voltage levels, enabling multiple current levels to be written to the memory cell. This dynamic adjustment allows a single memory cell structure to store multiple data levels without requiring additional physical structures.
Solution Approach 2:
The patent changes the electrical parameters (voltage levels) of the switch transistors to control the amount of current flowing through the memory cell. By varying the gate voltage of the column and row switches, different turn-on degrees are achieved, which directly controls the current magnitude. This parameter change enables multiple data levels to be stored in the same memory cell configuration.
2Quantity of substance
If process changes are implemented to achieve multiple-level data storage, then data storage capacity improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent achieves multiple-level data storage by changing operational voltage parameters rather than modifying the manufacturing process. The column and row switches are controlled with different voltage levels to produce different current magnitudes through the memory cell. This approach maintains the same fabrication process while enabling enhanced storage capacity through electrical parameter control.
Solution Approach 2:
The existing memory cell structure is made multi-functional by using it to store multiple data levels through voltage-controlled current modulation. The same physical structure that previously stored binary data now can represent multiple data levels by varying the current magnitude controlled through the switch transistors, eliminating the need for separate structures for different storage modes.
3Quantity of substance
If the turn-on degree of switches is adjusted to control current flow, then multiple-level data storage is enabled, but control complexity increases
Solution Approach 1:
The patent employs feedback mechanisms where the applied voltages to the column and row switches are controlled based on the desired data level to be written. By adjusting the gate voltages of the switches in response to write commands, the system achieves precise control over the current magnitude flowing through the memory cell, enabling reliable multiple-level data storage despite the increased control requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data storage capacity by enabling multiple-level data storage without requiring process changes, improving efficiency and flexibility in data management.
Implementation Method 1
a turn-on degree of the column switch and a turn-on degree of the row switch is changed... a turn-on degree of the first transistor is changed according to a level of a voltage applied to a gate of the first transistor
Data Source
AI summary
A semiconductor device may include a column switch that electrically connects a global bit line to a bit line or disconnects the global bit line from the bit line, a row switch that electrically connects a global word line to a word line or disconnects the global word line from the word line, and a memory cell electrically connected between the bit line and the word line. During a write operation, one or both of a turn-on degree of the column switch and the row switch may be changed.