Memory Cell Read-State Separation Based on Program Usage Frequency
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Solution Overview
Problem
Current artificial neural networks face challenges in high-performance information processing due to inadequate hardware technology, particularly in terms of energy efficiency and scalability, as they rely on bulky CMOS-implemented synapses and lack efficient methods for individual programming and erasure of non-volatile memory cells.
Innovation Solution
A neural network device utilizing a combination of CMOS technology and non-volatile memory arrays, where memory cells are programmed to varying program states based on frequency of use, allowing for individual programming, erasure, and read operations without disturbing other cells, enabling precise tuning of synapse weights and improving energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in the same location regardless of usage frequency, then storage structure is simple, but frequently accessed data experiences slower access speeds due to NAND flash memory characteristics
Solution Approach 1:
The storage device divides storage space into multiple zones (first storage zone for frequently accessed data, second storage zone for less frequently accessed data). This segmentation allows frequently accessed data to be stored in optimized locations with faster access characteristics, while maintaining overall system functionality through the divided structure.
Solution Approach 2:
Different regions of the storage device are assigned different characteristics and purposes. The first storage zone is optimized for frequent access with appropriate block structures and wear leveling, while the second storage zone handles less frequent access. This local differentiation optimizes overall performance by matching data access patterns to appropriate storage regions.
2Reliability
If wear leveling is applied uniformly across all data, then data protection is consistent, but frequently accessed data suffers from accelerated wear and reduced longevity
Solution Approach 1:
The storage device segments data storage into multiple zones with different wear leveling strategies. Frequently accessed data in the first storage zone receives targeted wear leveling management, while less frequently accessed data in the second storage zone has different wear characteristics. This segmentation allows the system to protect frequently accessed data from excessive wear while maintaining overall data reliability.
Solution Approach 2:
The system dynamically adjusts wear leveling parameters based on data access frequency. Frequently accessed data blocks receive enhanced wear leveling protection with adjusted allocation strategies, while less frequently accessed blocks use standard wear leveling. This parameter adjustment extends the lifespan of frequently accessed data while maintaining consistent reliability across all stored data.
3Productivity
If the storage device uses a single storage zone, then device structure is simple, but performance degrades over time due to uniform wear across all blocks
Solution Approach 1:
The storage device is divided into multiple zones (first storage zone and second storage zone) with different access patterns and management strategies. This segmentation maintains relatively simple device structure while improving performance by directing frequently accessed data to optimized zones, thereby reducing overall performance degradation over time.
Solution Approach 2:
The storage device implements dynamic zone management where data can be moved between zones based on access frequency. The controller dynamically adjusts which data resides in which zone, optimizing performance based on actual usage patterns while maintaining manageable device complexity through automated management.
Data Source
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AI summary
A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.