Master-Slave DRAM Reference Voltage Sharing for Lower Power
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Solution Overview
Problem
Dynamic random-access memory (DRAM) devices have high power consumption due to the need for DC current to provide reference voltages to memory chips.
Innovation Solution
The DRAM device incorporates slave DRAM chips with slave fuse circuits and slave reference voltage generators, and a master DRAM chip to control operations, enabling the slave DRAM chips to provide reference voltages through slave fuse setting operations, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory chips use DC current to provide reference voltages, then each chip can independently determine received signals, but power consumption increases
Solution Approach 1:
The system is segmented into a master DRAM chip and multiple slave DRAM chips. The master chip maintains full functionality with its own reference voltage generator, while slave chips have their reference voltage generators disabled during normal operation. This segmentation allows the system to maintain signal determination capability through the master chip while significantly reducing overall power consumption by eliminating redundant reference voltage generation in slave chips.
Solution Approach 2:
The master DRAM chip serves multiple functions: it acts as a normal memory chip for its own operations and simultaneously provides reference voltages to all slave chips through shared voltage lines. This multi-functionality eliminates the need for each slave chip to have its own active reference voltage generator, thereby reducing power consumption while maintaining the ability to determine received signals across all chips.
2Use of energy by moving object
If slave reference voltage generators are disabled to reduce power consumption, then power usage decreases, but signal determination capability may be affected
Solution Approach 1:
The master DRAM chip acts as an intermediary that generates and distributes reference voltages to all slave chips through shared voltage lines. This intermediary approach allows slave chips to receive the necessary reference voltages for signal determination without having their own active reference voltage generators, thus maintaining reliability while reducing power consumption.
Solution Approach 2:
The reference voltage generation function is merged from individual slave chips into the master chip. All slave chips share the reference voltages generated by the master chip through common voltage lines. This merging eliminates redundant power consumption in slave chips while ensuring that all chips have access to the necessary reference voltages for accurate signal determination.
Data Source
AI summary
A dynamic random-access memory (DRAM) device is provided. The DRAM device includes a plurality of slave DRAM chips and a master DRAM chip. Each of the plurality of slave DRAM chips includes a slave fuse circuit and a slave reference voltage generator. The slave fuse circuit provides a slave set signal according to a slave fuse setting operation of the slave fuse circuit. The slave reference voltage generator provides a slave reference voltage according to the slave set signal. The master DRAM chip controls operations of the plurality of slave DRAM chips.