NAND Flash Memory Page Buffer Architecture for Throughput
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Solution Overview
Problem
The limitations of traditional NAND flash memory architectures, where the number of page buffers is restricted due to their large circuit size, leading to limited read/write performance, as each page buffer is typically connected to only one or two bit lines, thereby restricting the number of bit lines that can be programmed or read simultaneously.
Innovation Solution
The introduction of bit line select gates that allow a page buffer to connect to multiple bit lines, enabling multiple-page programming and reading, along with additional pass gates and data registers to enhance operation, and novel programming and reading operations that increase performance without increasing the number of page buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of page buffers is increased to improve data read/write throughput, then memory performance is enhanced, but the die size increases significantly since page buffers occupy 20% to 40% of the memory's die size
Solution Approach 1:
A single page buffer is designed to serve multiple bit lines simultaneously through bit line select gates. The page buffer can selectively connect to different bit lines (e.g., BL0, BL1, BL2, BL3) based on control signals, enabling one page buffer to perform the function of multiple page buffers. This multi-functionality allows the system to maintain high data read/write throughput without proportionally increasing the number of page buffers and die size.
Solution Approach 2:
Bit line select gates are introduced as intermediary components between the page buffer and multiple bit lines. These select gates act as mediators that control the connection between the single page buffer and different bit lines, enabling selective data transfer to multiple bit lines. This intermediary structure allows one page buffer to efficiently manage multiple bit lines without requiring dedicated page buffers for each bit line, thus improving throughput while controlling die size.
2Productivity
If each page buffer is connected to only one or two bit lines as in traditional architecture, then the circuit design is simple, but the number of bit lines that can be programmed or read simultaneously is limited
Solution Approach 1:
The connection structure is segmented into controllable segments using bit line select gates. Instead of a fixed one-to-one or one-to-two connection, the page buffer connection is divided into multiple selectable segments that can be dynamically activated. Each select gate controls a segment of the connection to different bit lines, allowing the system to activate only the necessary segments for current operations, thereby increasing parallel processing capability while managing complexity through modular control.
Solution Approach 2:
The page buffer connection structure transitions from a static one-to-one or one-to-two connection to a dynamic multi-to-many connection. Bit line select gates enable the page buffer to dynamically switch connections to different bit lines based on operational requirements. This dynamic reconfigurability allows the same hardware structure to adapt to different programming and reading scenarios, significantly increasing the number of bit lines that can be processed simultaneously without proportionally increasing hardware complexity.
Data Source
AI summary
Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.