Stacked Semiconductor Memory Status Acquisition via Serial Signal Shifting
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently reading the status of multiple memory core chips stacked together, as the current methods require transmitting status read commands sequentially, leading to increased time and complexity in status information acquisition.
Innovation Solution
A semiconductor memory device configuration where a second chip outputs status information in a serial manner using a clock signal, with each NAND chip having a status output control circuit that shifts and synchronizes signals, allowing simultaneous status data collection from multiple chips sharing a chip enable signal, reducing the time required for status reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If status read commands are transmitted sequentially to multiple memory core chips, then the interface chip can check the status of each chip, but the time required for status information acquisition increases
Solution Approach 1:
The patent segments the status reading process by assigning unique chip enable signals to different memory core chips. Each chip's status can be read independently by activating its specific chip enable signal, allowing parallel status acquisition rather than sequential reading. This segmentation enables the interface chip to check multiple chips simultaneously, resolving the time consumption issue.
Solution Approach 2:
The patent merges multiple chip enable signals into a shared bus structure where each chip responds to its designated signal. By combining the status reading operations across multiple chips through a unified interface chip and common data bus, the system achieves efficient parallel status acquisition without requiring separate physical interfaces for each chip, thus reducing overall time while maintaining organization.
2Productivity
If multiple memory core chips are stacked together, then the device integration is improved, but the complexity of managing and reading status from each chip increases
Solution Approach 1:
Each memory core chip is assigned a unique chip enable signal identifier, creating distinct controllable segments within the stacked architecture. This segmentation allows the interface chip to selectively activate and manage individual chips or groups of chips, simplifying the management complexity despite high integration. The unique signaling ensures that each chip can be independently addressed and controlled.
Solution Approach 2:
The interface chip is designed with universal functionality to handle multiple memory core chips through a single interface. It can selectively enable different chips using chip enable signals, read status from any enabled chip, and manage operations across all stacked chips through a unified control mechanism. This multi-functionality reduces the need for separate management circuits for each chip, thereby reducing overall system complexity while maintaining high integration.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.