Flash Memory Sense Amplifier Switching for Parallel Verification
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Solution Overview
Problem
Conventional flash memory apparatuses require sequential performance of refresh verification and program verification, leading to significant verification time, which hampers the efficiency of erase operations.
Innovation Solution
The flash memory apparatus simultaneously performs refresh verification and program verification using two sense amplifiers during a refresh operation, reducing verification time through simultaneous comparison of threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If refresh verification and program verification are performed sequentially, then verification accuracy is maintained, but verification time increases significantly
Solution Approach 1:
The verification process is segmented into two parallel paths: refresh verification path and program verification path. Each path has its dedicated sense amplifier and reference voltage source, allowing independent simultaneous operation. The first sense amplifier compares threshold voltage with refresh reference voltage, while the second sense amplifier compares with program reference voltage, both occurring concurrently during the refresh operation.
Solution Approach 2:
The sense amplifier circuit is designed with multi-functionality to serve both refresh verification and program verification purposes. By configuring switches to connect different reference voltages to the same sense amplifier, the circuit can perform multiple verification types without requiring completely separate dedicated circuits for each function, thus reducing overall system complexity while enabling parallel verification.
2Productivity
If two sense amplifiers are used for simultaneous verification, then verification time is reduced, but circuit complexity increases
Solution Approach 1:
The patent merges the refresh verification and program verification operations into a single time window during the refresh operation. Both verifications share common circuit elements such as the memory cell array, bit lines, and control logic, while duplicating only the essential sensing components (sense amplifiers and reference voltages) needed for parallel operation. This combining approach achieves simultaneous verification without proportionally increasing overall circuit complexity.
Solution Approach 2:
The circuit employs dynamic switching mechanisms where switches can reconfigure the connections between sense amplifiers and reference voltages based on the verification mode required. This dynamic reconfiguration allows the same physical hardware to serve multiple verification functions at different times, reducing the need for permanently duplicated circuits and thereby controlling complexity while maintaining high verification throughput.
Data Source
AI summary
A flash memory apparatus includes a memory array, bit lines, a decoder, a sensing circuit, and a synchronous refresh switch circuit. The memory array includes a plurality of memory regions. Each of the memory regions includes a plurality of memory cells. The decoder selects target memory cells from the memory cells according to an address signal. The sensing circuit includes a plurality of sense amplifier groups. The synchronous refresh switch circuit includes a plurality of first synchronous refresh switches. The first synchronous refresh switches are respectively coupled between a first input terminal of a first sense amplifier and a first input terminal of a second sense amplifier of each of the sense amplifier groups. During a refresh operation, the first synchronous refresh switches are turned on to simultaneously perform a refresh verification and a program verification on the corresponding target memory cells.