3D Memory Channel Structure With Oxidized Buffer Layer Reliability

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Solution Overview

Problem

The operational reliability of three-dimensional semiconductor memory devices is compromised as more memory cells are stacked vertically, leading to deteriorated performance.

Innovation Solution

A semiconductor memory device design incorporating a core insulating layer, a semiconductor structure with a channel portion and capping portion, an oxidized buffer layer, and alternating conductive and insulating layers, along with a manufacturing method involving material layer stacking, opening formation, and gettering processes to enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If more memory cells are stacked vertically in a three-dimensional cell array, then storage capacity is improved, but operational reliability deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidoperational reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

An oxidized buffer layer is introduced as an intermediary layer between the core insulating layer and the semiconductor channel portion. This buffer layer, containing metal oxide, acts as a mediator to prevent direct harmful interaction between the core insulating layer and the semiconductor structure, thereby improving operational reliability while maintaining the vertical stacking configuration for high storage capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If more memory cells are stacked vertically, then storage capacity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvestorage capacityVSAvoidmanufacturing precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The oxidized buffer layer is formed in advance before the semiconductor structure is fully assembled. By pre-forming this protective layer with metal oxide, the patent prepares the interface in advance to prevent potential manufacturing defects and reliability issues that could arise from direct contact between the core insulating layer and semiconductor channels in high-density vertical stacking.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If metal catalysts are used in the manufacturing process, then crystallization is enhanced, but harmful factors are introduced

Engineering Contradiction:
Improvecrystallization uniformityVSAvoidmetal catalyst-induced issues
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent converts the potentially harmful metal catalysts into a beneficial oxidized buffer layer. By oxidizing the metal catalysts that were used during crystallization, the harmful residual metal catalysts are transformed into a protective oxidized buffer layer containing metal oxide, which improves operational reliability while maintaining the benefits of uniform crystallization.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed design and manufacturing method improve operational reliability by ensuring uniform crystallization and reducing metal catalyst-induced issues, enhancing the performance of three-dimensional memory devices.

Implementation Method 1

forming an oxidized buffer layer by oxidizing the buffer layer exposed after the gettering process

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS20260032899A1Semiconductor memory device and manufacturing method of the semiconductor memory device
Publication Date: 2026.01.29 SK HYNIX INC
  • US20260032899A1 patent drawing
  • US20260032899A1 patent drawing
  • US20260032899A1 patent drawing

AI summary

The present disclosure relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a core insulating layer, a semiconductor structure including a channel portion on a side wall of the core insulating layer and a capping portion covering one surface of the core insulating layer and coupled to the channel portion, a plurality of conductive layers and a plurality of insulating layers surrounding a side wall of the semiconductor structure, each of the plurality of conductive layers and each of the plurality of insulating layers alternating with each other, and a memory layer disposed between each of the plurality of conductive layers and the semiconductor structure.