Page Buffer Sensing Node Split for Low-Voltage NAND Read Margins
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Solution Overview
Problem
The challenge of maintaining both on-cell and off-cell margins in non-volatile memory devices becomes difficult as the operating voltage decreases, leading to fluctuations in trip voltage and making it hard to accurately determine the state of memory cells.
Innovation Solution
The implementation of a separated sensing node structure in the page buffer, utilizing a separation transistor to divide the sensing node into two parts, allows for the separation of sensing and latching operations, thereby controlling the trip voltages and securing both on-cell and off-cell margins even at low operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the operating voltage of the page buffer is decreased to implement low-power NAND flash memory, then power consumption is reduced, but the voltage range at the sensing node decreases and trip voltage variation increases, making it difficult to correctly determine memory cell states
Solution Approach 1:
The sensing node is divided into two separate sensing nodes: a first sensing node for sensing the memory cell state and a second sensing node for latching the data. This segmentation allows independent optimization of sensing and latching operations, enabling accurate data determination even at low operating voltages where traditional single-node designs fail to provide sufficient voltage range and trip voltage stability
Solution Approach 2:
A separation transistor is introduced as an intermediary component between the first and second sensing nodes. This transistor selectively transmits the voltage developed at the first sensing node to the second sensing node based on the sensing trip voltage, acting as a controlled mediator that enables reliable data transfer and latching while maintaining distinct voltage ranges for sensing and latching operations
2Area of stationary object
If the area of the page buffer is decreased to improve integration, then device size is reduced, but the variation of trip voltage increases, making it difficult to correctly determine memory cell states
Solution Approach 1:
By segmenting the sensing node into first and second sensing nodes with distinct functions, the invention reduces the area required for each individual node while maintaining adequate voltage ranges. The separation transistor enables compact integration by controlling voltage transmission between the two nodes, achieving both area reduction and improved trip voltage control through the specialized sensing-latching architecture
Data Source
AI summary
Disclosed is a non-volatile memory device comprising, a cell array including memory cells connected to a bit line, a page buffer including a sensing node for sensing a memory cell selected through the bit line, and a control circuit configured to control a sensing operation of the page buffer, wherein the page buffer comprises, a separation transistor configured to separate the sensing node into a first sensing node and a second sensing node, and selectively transmit a voltage developed at the first sensing node to the second sensing node, and a sensing latch configured to latch data according to a voltage level of the second sensing node.